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Re: [Qemu-devel] [PATCH 13/15] ppc4xx: Add more PLB registers


From: David Gibson
Subject: Re: [Qemu-devel] [PATCH 13/15] ppc4xx: Add more PLB registers
Date: Wed, 23 Aug 2017 12:39:45 +1000
User-agent: Mutt/1.8.3 (2017-05-23)

On Sun, Aug 20, 2017 at 07:23:05PM +0200, BALATON Zoltan wrote:
> These registers are present in 440 SoCs (and maybe in others too) and
> U-Boot accesses them when printing register info. We don't emulate
> these but add them to avoid crashing when they are read or written.
> 
> Signed-off-by: BALATON Zoltan <address@hidden>

I'm ok with stub implementation, but I'm a bit uncomfortable with
registering these DCRs unconditionally rather than just on the chips
that actually implement them.

> ---
>  hw/ppc/ppc405_uc.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index e621d0a..8e58065 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -105,9 +105,12 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, 
> ppc4xx_bd_info_t *bd,
>  
> /*****************************************************************************/
>  /* Peripheral local bus arbitrer */
>  enum {
> -    PLB0_BESR = 0x084,
> -    PLB0_BEAR = 0x086,
> -    PLB0_ACR  = 0x087,
> +    PLB3A0_ACR = 0x077,
> +    PLB4A0_ACR = 0x081,
> +    PLB0_BESR  = 0x084,
> +    PLB0_BEAR  = 0x086,
> +    PLB0_ACR   = 0x087,
> +    PLB4A1_ACR = 0x089,
>  };
>  
>  typedef struct ppc4xx_plb_t ppc4xx_plb_t;
> @@ -179,9 +182,12 @@ void ppc4xx_plb_init(CPUPPCState *env)
>      ppc4xx_plb_t *plb;
>  
>      plb = g_malloc0(sizeof(ppc4xx_plb_t));
> +    ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> +    ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
>      ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
>      ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
>      ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
> +    ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
>      qemu_register_reset(ppc4xx_plb_reset, plb);
>  }
>  

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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