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[Qemu-devel] [PULL 8/8] target/mips: Fix RDHWR CC with icount
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PULL 8/8] target/mips: Fix RDHWR CC with icount |
Date: |
Thu, 3 Aug 2017 15:45:15 +0100 |
From: James Hogan <address@hidden>
RDHWR CC reads the CPU timer like MFC0 CP0_Count, so with icount enabled
it must set can_do_io while it calls the helper to avoid the "Bad icount
read" error. It should also break out of the translation loop to ensure
that timer interrupts are immediately handled.
Fixes: 2e70f6efa8b9 ("Add instruction counter.")
Signed-off-by: James Hogan <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Yongbok Kim <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
---
target/mips/translate.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bcea2a1..c78d272 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -10755,8 +10755,19 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int
rd, int sel)
gen_store_gpr(t0, rt);
break;
case 2:
+ if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_rdhwr_cc(t0, cpu_env);
+ if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
gen_store_gpr(t0, rt);
+ /* Break the TB to be able to take timer interrupts immediately
+ after reading count. BS_STOP isn't sufficient, we need to ensure
+ we break completely out of translated code. */
+ gen_save_pc(ctx->pc + 4);
+ ctx->bstate = BS_EXCP;
break;
case 3:
gen_helper_rdhwr_ccres(t0, cpu_env);
--
2.7.4
- [Qemu-devel] [PULL 0/8] target-mips queue, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 2/8] mips/malta: leave space for the bootmap after the initrd, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 1/8] target-mips: Don't stop on [d]mtc0 DESAVE/KScratch, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 7/8] target/mips: Drop redundant gen_io_start/stop(), Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 5/8] target-mips: apply CP0.PageMask before writing into TLB entry, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 4/8] mips: Add KVM T&E segment support for TCG, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 3/8] mips: Improve segment defs for KVM T&E guests, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 8/8] target/mips: Fix RDHWR CC with icount,
Yongbok Kim <=
- [Qemu-devel] [PULL 6/8] target/mips: Use BS_EXCP where interrupts are expected, Yongbok Kim, 2017/08/03
- Re: [Qemu-devel] [PULL 0/8] target-mips queue, Peter Maydell, 2017/08/04