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[Qemu-devel] [RFC PATCH for 2.11 10/23] target/arm/translate-a64.c: hand
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [RFC PATCH for 2.11 10/23] target/arm/translate-a64.c: handle_3same_64 comment fix |
Date: |
Thu, 20 Jul 2017 16:04:13 +0100 |
We do implement all the opcodes.
Signed-off-by: Alex Bennée <address@hidden>
---
target/arm/translate-a64.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e55547d95d..68099fdb5e 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7135,8 +7135,7 @@ static void handle_3same_64(DisasContext *s, int opcode,
bool u,
/* Handle 64x64->64 opcodes which are shared between the scalar
* and vector 3-same groups. We cover every opcode where size == 3
* is valid in either the three-reg-same (integer, not pairwise)
- * or scalar-three-reg-same groups. (Some opcodes are not yet
- * implemented.)
+ * or scalar-three-reg-same groups.
*/
TCGCond cond;
--
2.13.0
- [Qemu-devel] [RFC PATCH for 2.11 00/23] Implementing FP16 for ARMv8.2 using SoftFloat2a and 3c, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 10/23] target/arm/translate-a64.c: handle_3same_64 comment fix,
Alex Bennée <=
- [Qemu-devel] [RFC PATCH for 2.11 13/23] target/arm/translate-a64.c: add FP16 FADD to AdvSIMD 3 Same, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 08/23] target-aarch64: enable SoftFloat3 build for FP16, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 09/23] arm: introduce ARM_V8_FP16 feature bit, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 11/23] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 17/23] fpu/softfloat2a: implement propagateFloat16NaN, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/20