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[Qemu-devel] [PATCH v3 12/30] target/sh4: Pass DisasContext to fpr64 rou
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 12/30] target/sh4: Pass DisasContext to fpr64 routines |
Date: |
Tue, 18 Jul 2017 10:02:37 -1000 |
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/sh4/translate.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index b3c3e8e..caa4598 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -336,12 +336,12 @@ static void gen_delayed_conditional_jump(DisasContext *
ctx)
gen_jump(ctx);
}
-static inline void gen_load_fpr64(TCGv_i64 t, int reg)
+static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
}
-static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
+static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t);
}
@@ -984,8 +984,8 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_SZ) {
TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XHACK(B7_4));
- gen_store_fpr64(fp, XHACK(B11_8));
+ gen_load_fpr64(ctx, fp, XHACK(B7_4));
+ gen_store_fpr64(ctx, fp, XHACK(B11_8));
tcg_temp_free_i64(fp);
} else {
tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4));
@@ -1094,8 +1094,8 @@ static void _decode_opc(DisasContext * ctx)
break; /* illegal instruction */
fp0 = tcg_temp_new_i64();
fp1 = tcg_temp_new_i64();
- gen_load_fpr64(fp0, DREG(B11_8));
- gen_load_fpr64(fp1, DREG(B7_4));
+ gen_load_fpr64(ctx, fp0, DREG(B11_8));
+ gen_load_fpr64(ctx, fp1, DREG(B7_4));
switch (ctx->opcode & 0xf00f) {
case 0xf000: /* fadd Rm,Rn */
gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1);
@@ -1116,7 +1116,7 @@ static void _decode_opc(DisasContext * ctx)
gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1);
return;
}
- gen_store_fpr64(fp0, DREG(B11_8));
+ gen_store_fpr64(ctx, fp0, DREG(B11_8));
tcg_temp_free_i64(fp0);
tcg_temp_free_i64(fp1);
} else {
@@ -1701,7 +1701,7 @@ static void _decode_opc(DisasContext * ctx)
break; /* illegal instruction */
fp = tcg_temp_new_i64();
gen_helper_float_DT(fp, cpu_env, cpu_fpul);
- gen_store_fpr64(fp, DREG(B11_8));
+ gen_store_fpr64(ctx, fp, DREG(B11_8));
tcg_temp_free_i64(fp);
}
else {
@@ -1715,7 +1715,7 @@ static void _decode_opc(DisasContext * ctx)
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, DREG(B11_8));
+ gen_load_fpr64(ctx, fp, DREG(B11_8));
gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp);
tcg_temp_free_i64(fp);
}
@@ -1737,9 +1737,9 @@ static void _decode_opc(DisasContext * ctx)
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, DREG(B11_8));
+ gen_load_fpr64(ctx, fp, DREG(B11_8));
gen_helper_fsqrt_DT(fp, cpu_env, fp);
- gen_store_fpr64(fp, DREG(B11_8));
+ gen_store_fpr64(ctx, fp, DREG(B11_8));
tcg_temp_free_i64(fp);
} else {
gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8));
@@ -1765,7 +1765,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv_i64 fp = tcg_temp_new_i64();
gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul);
- gen_store_fpr64(fp, DREG(B11_8));
+ gen_store_fpr64(ctx, fp, DREG(B11_8));
tcg_temp_free_i64(fp);
}
return;
@@ -1773,7 +1773,7 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
{
TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, DREG(B11_8));
+ gen_load_fpr64(ctx, fp, DREG(B11_8));
gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp);
tcg_temp_free_i64(fp);
}
--
2.9.4
- [Qemu-devel] [PATCH v3 02/30] target/sh4: Consolidate end-of-TB tests, (continued)
- [Qemu-devel] [PATCH v3 02/30] target/sh4: Consolidate end-of-TB tests, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 01/30] target/sh4: Use cmpxchg for movco, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 03/30] target/sh4: Introduce TB_FLAG_ENVFLAGS_MASK, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 04/30] target/sh4: Keep env->flags clean, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 05/30] target/sh4: Adjust TB_FLAG_PENDING_MOVCA, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 06/30] target/sh4: Handle user-space atomics, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 07/30] target/sh4: Recognize common gUSA sequences, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 08/30] linux-user/sh4: Notice gUSA regions during signal delivery, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 09/30] linux-user/sh4: Clean env->flags on signal boundaries, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 10/30] target/sh4: Hoist register bank selection, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 12/30] target/sh4: Pass DisasContext to fpr64 routines,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 11/30] target/sh4: Unify cpu_fregs into FREG, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 14/30] target/sh4: Eliminate unused XREG macro, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 16/30] target/sh4: Load/store Dr as 64-bit quantities, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 17/30] target/sh4: Simplify 64-bit fp reg-reg move, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 18/30] target/sh4: Unify code for CHECK_NOT_DELAY_SLOT, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 15/30] target/sh4: Merge DREG into fpr64 routines, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 19/30] target/sh4: Unify code for CHECK_PRIVILEGED, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 20/30] target/sh4: Unify code for CHECK_FPU_ENABLED, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 21/30] target/sh4: Tidy misc illegal insn checks, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 22/30] target/sh4: Introduce CHECK_FPSCR_PR_*, Richard Henderson, 2017/07/18