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Re: [Qemu-devel] [PATCH 5/8] apb: fix endianness for APB and PCI config
From: |
Mark Cave-Ayland |
Subject: |
Re: [Qemu-devel] [PATCH 5/8] apb: fix endianness for APB and PCI config accesses |
Date: |
Fri, 14 Jul 2017 11:01:48 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 |
On 12/07/17 10:09, Artyom Tarasenko wrote:
> On Tue, Jul 11, 2017 at 11:53 PM, Mark Cave-Ayland
> <address@hidden> wrote:
>> Signed-off-by: Mark Cave-Ayland <address@hidden>
>> ---
>> hw/pci-host/apb.c | 6 ++----
>> 1 file changed, 2 insertions(+), 4 deletions(-)
>>
>> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
>> index 622c341..5ad7678 100644
>> --- a/hw/pci-host/apb.c
>> +++ b/hw/pci-host/apb.c
>> @@ -561,7 +561,7 @@ static uint64_t apb_config_readl (void *opaque,
>> static const MemoryRegionOps apb_config_ops = {
>> .read = apb_config_readl,
>> .write = apb_config_writel,
>> - .endianness = DEVICE_NATIVE_ENDIAN,
>> + .endianness = DEVICE_BIG_ENDIAN,
>
> Is this correct? I thought all the PCI config registers are always
> little-endian.
Yes - these are the registers on the APB itself...
>> };
>>
>> static void apb_pci_config_write(void *opaque, hwaddr addr,
>> @@ -570,7 +570,6 @@ static void apb_pci_config_write(void *opaque, hwaddr
>> addr,
>> APBState *s = opaque;
>> PCIHostState *phb = PCI_HOST_BRIDGE(s);
>>
>> - val = qemu_bswap_len(val, size);
>> APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
>> addr, val);
>> pci_data_write(phb->bus, addr, val, size);
>> }
>> @@ -583,7 +582,6 @@ static uint64_t apb_pci_config_read(void *opaque, hwaddr
>> addr,
>> PCIHostState *phb = PCI_HOST_BRIDGE(s);
>>
>> ret = pci_data_read(phb->bus, addr, size);
>> - ret = qemu_bswap_len(ret, size);
>> APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
>> return ret;
>> }
>> @@ -744,7 +742,7 @@ static void pci_pbm_reset(DeviceState *d)
>> static const MemoryRegionOps pci_config_ops = {
>> .read = apb_pci_config_read,
>> .write = apb_pci_config_write,
>> - .endianness = DEVICE_NATIVE_ENDIAN,
>> + .endianness = DEVICE_LITTLE_ENDIAN,
... while these are the PCI config registers. It's this endian change
here that makes it possible to remove the qemu_bswap_len() calls
included in the diff above.
ATB,
Mark.
- Re: [Qemu-devel] [PATCH 4/8] apb: fix up PCI bus nomenclature, (continued)
- [Qemu-devel] [PATCH 3/8] sun4u: expose fw_cfg and NVRAM on ebus PCI IO address space, Mark Cave-Ayland, 2017/07/11
- [Qemu-devel] [PATCH 7/8] sun4u: create single default onboard ne2k_pci NIC for machine, Mark Cave-Ayland, 2017/07/11
- [Qemu-devel] [PATCH 6/8] apb: add busA qdev property to PBM PCI bridge, Mark Cave-Ayland, 2017/07/11
- [Qemu-devel] [PATCH 8/8] sun4u: move in-built devices behind PCI bridge A, Mark Cave-Ayland, 2017/07/11
- [Qemu-devel] [PATCH 1/8] sun4u: pass PCIDevice into pci_ebus_init() instead of PCIBus, Mark Cave-Ayland, 2017/07/11
- [Qemu-devel] [PATCH 5/8] apb: fix endianness for APB and PCI config accesses, Mark Cave-Ayland, 2017/07/11
- Re: [Qemu-devel] [PATCH 0/8] sun4u: change PCI topology to better match a real Ultra 5, no-reply, 2017/07/11