[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 10/27] target/sh4: Hoist register bank selection
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 10/27] target/sh4: Hoist register bank selection |
Date: |
Thu, 6 Jul 2017 16:20:54 -1000 |
Compute which register bank to use once at the start of translation.
Signed-off-by: Richard Henderson <address@hidden>
---
target/sh4/translate.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 73b3e02..0ac101e 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -41,6 +41,7 @@ typedef struct DisasContext {
uint32_t envflags; /* should stay in sync with env->flags using TCG ops
*/
int bstate;
int memidx;
+ int gbank;
uint32_t delayed_pc;
int singlestep_enabled;
uint32_t features;
@@ -64,7 +65,7 @@ enum {
/* global register indexes */
static TCGv_env cpu_env;
-static TCGv cpu_gregs[24];
+static TCGv cpu_gregs[32];
static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t;
static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr;
static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
@@ -99,16 +100,19 @@ void sh4_translate_init(void)
"FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
};
- if (done_init)
+ if (done_init) {
return;
+ }
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
tcg_ctx.tcg_env = cpu_env;
- for (i = 0; i < 24; i++)
+ for (i = 0; i < 24; i++) {
cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, gregs[i]),
gregnames[i]);
+ }
+ memcpy(cpu_gregs + 24, cpu_gregs + 8, 8 * sizeof(TCGv));
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, pc), "PC");
@@ -359,13 +363,8 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
#define B11_8 ((ctx->opcode >> 8) & 0xf)
#define B15_12 ((ctx->opcode >> 12) & 0xf)
-#define REG(x) ((x) < 8 && (ctx->tbflags & (1u << SR_MD))\
- && (ctx->tbflags & (1u << SR_RB))\
- ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
-
-#define ALTREG(x) ((x) < 8 && (!(ctx->tbflags & (1u << SR_MD))\
- || !(ctx->tbflags & (1u << SR_RB)))\
- ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
+#define REG(x) cpu_gregs[(x) ^ ctx->gbank]
+#define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10]
#define FREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))
#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
@@ -2272,6 +2271,8 @@ void gen_intermediate_code(CPUSH4State * env, struct
TranslationBlock *tb)
ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.features = env->features;
ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);
+ ctx.gbank = ((ctx.tbflags & (1 << SR_MD)) &&
+ (ctx.tbflags & (1 << SR_RB))) * 0x10;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
--
2.9.4
- [Qemu-devel] Fwd: [PATCH v2.5] fixup! linux-user/sh4: Notice gUSA regions during signal delivery, (continued)
Re: [Qemu-devel] [PATCH v2 08/27] linux-user/sh4: Notice gUSA regions during signal delivery, Laurent Vivier, 2017/07/07
Re: [Qemu-devel] [PATCH v2 08/27] linux-user/sh4: Notice gUSA regions during signal delivery, Aurelien Jarno, 2017/07/15
[Qemu-devel] [PATCH v2 09/27] linux-user/sh4: Clean env->flags on signal boundaries, Richard Henderson, 2017/07/06
[Qemu-devel] [PATCH v2 10/27] target/sh4: Hoist register bank selection,
Richard Henderson <=
[Qemu-devel] [PATCH v2 11/27] target/sh4: Unify cpu_fregs into FREG, Richard Henderson, 2017/07/06
[Qemu-devel] [PATCH v2 12/27] target/sh4: Pass DisasContext to fpr64 routines, Richard Henderson, 2017/07/06
[Qemu-devel] [PATCH v2 13/27] target/sh4: Hoist fp register bank selection, Richard Henderson, 2017/07/06
[Qemu-devel] [PATCH v2 14/27] target/sh4: Eliminate unused XREG macro, Richard Henderson, 2017/07/06