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[Qemu-devel] [Intel-gfx][RFC 3/9] drm/i915/gvt: Adjust the gma parameter
From: |
Yulei Zhang |
Subject: |
[Qemu-devel] [Intel-gfx][RFC 3/9] drm/i915/gvt: Adjust the gma parameter in gpu commands during command parser |
Date: |
Mon, 26 Jun 2017 08:59:13 -0000 |
Adjust the gma parameter in gpu commands according to the shift
offset in guests' aperture and hidden gm address, and patch
the commands before submit to execute.
Signed-off-by: Yulei Zhang <address@hidden>
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 51241de5..540ee42 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -922,7 +922,7 @@ static int cmd_handler_lrr(struct parser_exec_state *s)
}
static inline int cmd_address_audit(struct parser_exec_state *s,
- unsigned long guest_gma, int op_size, bool index_mode);
+ unsigned long guest_gma, int op_size, bool index_mode, int
offset);
static int cmd_handler_lrm(struct parser_exec_state *s)
{
@@ -942,7 +942,7 @@ static int cmd_handler_lrm(struct parser_exec_state *s)
gma = cmd_gma(s, i + 1);
if (gmadr_bytes == 8)
gma |= (cmd_gma_hi(s, i + 2)) << 32;
- ret |= cmd_address_audit(s, gma, sizeof(u32), false);
+ ret |= cmd_address_audit(s, gma, sizeof(u32), false, i
+ 1);
}
i += gmadr_dw_number(s) + 1;
}
@@ -962,7 +962,7 @@ static int cmd_handler_srm(struct parser_exec_state *s)
gma = cmd_gma(s, i + 1);
if (gmadr_bytes == 8)
gma |= (cmd_gma_hi(s, i + 2)) << 32;
- ret |= cmd_address_audit(s, gma, sizeof(u32), false);
+ ret |= cmd_address_audit(s, gma, sizeof(u32), false, i
+ 1);
}
i += gmadr_dw_number(s) + 1;
}
@@ -1032,7 +1032,7 @@ static int cmd_handler_pipe_control(struct
parser_exec_state *s)
if (cmd_val(s, 1) & (1 << 21))
index_mode = true;
ret |= cmd_address_audit(s, gma, sizeof(u64),
- index_mode);
+ index_mode, 2);
}
}
}
@@ -1364,10 +1364,12 @@ static unsigned long get_gma_bb_from_cmd(struct
parser_exec_state *s, int index)
}
static inline int cmd_address_audit(struct parser_exec_state *s,
- unsigned long guest_gma, int op_size, bool index_mode)
+ unsigned long guest_gma, int op_size, bool index_mode, int
offset)
{
struct intel_vgpu *vgpu = s->vgpu;
u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
+ int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
+ u64 host_gma;
int i;
int ret;
@@ -1387,6 +1389,14 @@ static inline int cmd_address_audit(struct
parser_exec_state *s,
guest_gma + op_size - 1))) {
ret = -EINVAL;
goto err;
+ } else
+ intel_gvt_ggtt_gmadr_g2h(vgpu, guest_gma, &host_gma);
+
+ if (offset > 0) {
+ patch_value(s, cmd_ptr(s, offset), host_gma & GENMASK(31, 2));
+ if (gmadr_bytes == 8)
+ patch_value(s, cmd_ptr(s, offset + 1),
+ (host_gma >> 32) & GENMASK(15, 0));
}
return 0;
err:
@@ -1429,7 +1439,7 @@ static int cmd_handler_mi_store_data_imm(struct
parser_exec_state *s)
gma = (gma_high << 32) | gma_low;
core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
}
- ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
+ ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false, 1);
return ret;
}
@@ -1473,7 +1483,7 @@ static int cmd_handler_mi_op_2f(struct parser_exec_state
*s)
gma_high = cmd_val(s, 2) & GENMASK(15, 0);
gma = (gma_high << 32) | gma;
}
- ret = cmd_address_audit(s, gma, op_size, false);
+ ret = cmd_address_audit(s, gma, op_size, false, 1);
return ret;
}
@@ -1513,7 +1523,7 @@ static int cmd_handler_mi_flush_dw(struct
parser_exec_state *s)
/* Store Data Index */
if (cmd_val(s, 0) & (1 << 21))
index_mode = true;
- ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
+ ret = cmd_address_audit(s, (gma | (1 << 2)), sizeof(u64),
index_mode, 1);
}
/* Check notify bit */
if ((cmd_val(s, 0) & (1 << 8)))
--
2.7.4
- [Qemu-devel] [Intel-gfx][RFC 0/9] drm/i915/gvt: Add the live migration support to VFIO mdev deivce - Intel vGPU, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 2/9] drm/i915/gvt: Apply g2h adjustment during fence mmio access, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 6/9] drm/i915/gvt: Introduce new flag to indicate migration capability, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 3/9] drm/i915/gvt: Adjust the gma parameter in gpu commands during command parser,
Yulei Zhang <=
- [Qemu-devel] [Intel-gfx][RFC 8/9] drm/i915/gvt: Introduce new VFIO ioctl for mdev device dirty page sync, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 7/9] drm/i915/gvt: Introduce new VFIO ioctl for device status control, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 4/9] drm/i915/gvt: Retrieve the guest gm base address from PVINFO, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 1/9] drm/i915/gvt: Apply g2h adjust for GTT mmio access, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 5/9] drm/i915/gvt: Align the guest gm aperture start offset for live migration, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 9/9] drm/i915/gvt: Add support to VFIO region VFIO_PCI_DEVICE_STATE_REGION_INDEX, Yulei Zhang, 2017/06/26