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[Qemu-devel] [PATCH v1 7/8] target-microblaze: Introduce a use-msr-instr
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 7/8] target-microblaze: Introduce a use-msr-instr property |
Date: |
Tue, 20 Jun 2017 17:51:25 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Introduce a use-msr-instr property making msr instructions
optional.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/cpu.c | 5 +++--
target/microblaze/cpu.h | 1 +
target/microblaze/translate.c | 2 +-
3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 70e4743..bc96505 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -157,7 +157,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
| PVR2_D_LMB_MASK \
| PVR2_I_OPB_MASK \
| PVR2_I_LMB_MASK \
- | PVR2_USE_MSR_INSTR \
| PVR2_USE_PCMP_INSTR \
| PVR2_FPU_EXC_MASK \
| 0;
@@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
(cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
(cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
- (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0);
+ (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
+ (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0);
env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
PVR5_DCACHE_WRITEBACK_MASK : 0;
@@ -241,6 +241,7 @@ static Property mb_properties[] = {
DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
+ DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
false),
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e202229..5c960d0 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -301,6 +301,7 @@ struct MicroBlazeCPU {
uint8_t use_hw_mul;
bool use_barrel;
bool use_div;
+ bool use_msr_instr;
bool use_mmu;
bool dcache_writeback;
bool endi;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 36caa03..bb1bdfa 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -443,7 +443,7 @@ static void dec_msr(DisasContext *dc)
LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
dc->rd, dc->imm);
- if (!(dc->cpu->env.pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
+ if (!dc->cpu->cfg.use_msr_instr) {
/* nop??? */
return;
}
--
2.7.4
- Re: [Qemu-devel] [PATCH v1 2/8] target-microblaze: Don't hard code 0xb as initial MB version, (continued)
- [Qemu-devel] [PATCH v1 1/8] target-microblaze: Correct bit shift for the PVR0 version field, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 3/8] target-microblaze: Add CPU versions 9.4, 9.5 and 9.6, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 5/8] target-microblaze: Introduce a use-div property, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 4/8] target-microblaze: Introduce a use-barrel property, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 7/8] target-microblaze: Introduce a use-msr-instr property,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v1 6/8] target-microblaze: Introduce a use-hw-mul property, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 8/8] target-microblaze: Introduce a use-pcmp-instr property, Edgar E. Iglesias, 2017/06/20