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[Qemu-devel] [PATCH 1/3] Guess L1 cache linesize for aarch64
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 1/3] Guess L1 cache linesize for aarch64 |
Date: |
Thu, 8 Jun 2017 22:36:02 -0700 |
Using the cache hierarchy linesize minimum in CTR_EL0.
See the comment within the code for rationale.
* sysdeps/unix/sysv/linux/aarch64/sysconf.c: New file.
Cc: Marcus Shawcroft <address@hidden>
---
sysdeps/unix/sysv/linux/aarch64/sysconf.c | 55 +++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 sysdeps/unix/sysv/linux/aarch64/sysconf.c
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
new file mode 100644
index 0000000..30608dd
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -0,0 +1,55 @@
+/* Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <unistd.h>
+
+
+static long int linux_sysconf (int name);
+
+/* Get the value of the system variable NAME. */
+long int
+__sysconf (int name)
+{
+ unsigned ctr;
+
+ /* Unfortunately, the registers that contain the actual cache info
+ (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux
+ kernel (though they need not have been). However, CTR_EL0 contains
+ the *minimum* linesize in the entire cache hierarchy, and is
+ accessible to userland, for use in __aarch64_sync_cache_range,
+ and it is a reasonable assumption that the L1 cache will have that
+ minimum line size. */
+ switch (name)
+ {
+ case _SC_LEVEL1_ICACHE_LINESIZE:
+ asm("mrs\t%0, ctr_el0" : "=r"(ctr));
+ return 4 << (ctr & 0xf);
+ case _SC_LEVEL1_DCACHE_LINESIZE:
+ asm("mrs\t%0, ctr_el0" : "=r"(ctr));
+ return 4 << ((ctr >> 16) & 0xf);
+ }
+
+ return linux_sysconf (name);
+}
+
+/* Now the generic Linux version. */
+#undef __sysconf
+#define __sysconf static linux_sysconf
+#include <sysdeps/unix/sysv/linux/sysconf.c>
--
2.9.4
- [Qemu-devel] [PATCH v5 0/7] tcg: allocate TB structs preceding translate, Richard Henderson, 2017/06/09
- [Qemu-devel] [PATCH 1/3] Guess L1 cache linesize for aarch64,
Richard Henderson <=
- [Qemu-devel] [PATCH v5 0/7] tcg: allocate TB structs preceding translate, Richard Henderson, 2017/06/09
- [Qemu-devel] [PATCH v5 0/7] tcg: allocate TB structs preceding translate, Richard Henderson, 2017/06/09
- [Qemu-devel] [PATCH v5 3/7] tcg/aarch64: Use ADR in tcg_out_movi, Richard Henderson, 2017/06/09
- [Qemu-devel] [PATCH v5 1/7] util: add cacheinfo, Richard Henderson, 2017/06/09
- [Qemu-devel] [PATCH v5 4/7] tcg/arm: Use indirect branch for goto_tb, Richard Henderson, 2017/06/09
- [Qemu-devel] [PATCH v5 2/7] tcg: allocate TB structs before the corresponding translated code, Richard Henderson, 2017/06/09
- [Qemu-devel] [PATCH v5 5/7] tcg/arm: Remove limit on code buffer size, Richard Henderson, 2017/06/09
- [Qemu-devel] [PATCH v5 6/7] tcg/arm: Try pc-relative addresses for movi, Richard Henderson, 2017/06/09
- [Qemu-devel] [PATCH v5 7/7] tcg/arm: Use ldr (literal) for goto_tb, Richard Henderson, 2017/06/09
- Re: [Qemu-devel] [PATCH v5 0/7] tcg: allocate TB structs preceding translate, no-reply, 2017/06/09