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[Qemu-devel] [PATCH v5 7/9] ppc/pnv: create the ICP object under PnvCore
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH v5 7/9] ppc/pnv: create the ICP object under PnvCore |
Date: |
Mon, 3 Apr 2017 09:46:03 +0200 |
Each thread of a core is linked to an ICP. This allocates a PnvICPState
object before the PowerPCCPU object is realized and lets the XICSFabric
do the store under the 'intc' backlink when xics_cpu_setup() is
called.
This modeling removes the need of maintaining an array of ICP objects
under the PowerNV machine and also simplifies the XICSFabric icp_get()
handler.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
---
Changes since v4:
- moved the creation of PnvICPState object before the PowerPCCPU
object is realized to handle correctly errors.
Changes since v3:
- removed the array of ICP objects from under the PowerNV machine and
handled the allocation of the PnvICPState object for each thread
when the PowerPCCPU object is realized.
hw/ppc/pnv.c | 2 ++
hw/ppc/pnv_core.c | 27 +++++++++++++++++++++++++--
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 1c0672cbeb40..ab079ac60af5 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -694,6 +694,8 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(pnv_core),
pcc->core_pir(chip, core_hwid),
"pir", &error_fatal);
+ object_property_add_const_link(OBJECT(pnv_core), "xics",
+ qdev_get_machine(), &error_fatal);
object_property_set_bool(OBJECT(pnv_core), true, "realized",
&error_fatal);
object_unref(OBJECT(pnv_core));
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index d79d530b4881..1b7ec70f033d 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -25,6 +25,7 @@
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/xics.h"
static void powernv_cpu_reset(void *opaque)
{
@@ -110,23 +111,37 @@ static const MemoryRegionOps pnv_core_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_core_realize_child(Object *child, Error **errp)
+static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp)
{
Error *local_err = NULL;
CPUState *cs = CPU(child);
PowerPCCPU *cpu = POWERPC_CPU(cs);
+ Object *obj;
+
+ obj = object_new(TYPE_PNV_ICP);
+ object_property_add_child(OBJECT(cpu), "icp", obj, NULL);
+ object_property_add_const_link(obj, "xics", OBJECT(xi), &error_abort);
+ object_property_set_bool(obj, true, "realized", &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
object_property_set_bool(child, true, "realized", &local_err);
if (local_err) {
+ object_unparent(obj);
error_propagate(errp, local_err);
return;
}
powernv_cpu_init(cpu, &local_err);
if (local_err) {
+ object_unparent(obj);
error_propagate(errp, local_err);
return;
}
+
+ xics_cpu_setup(xi, cpu, ICP(obj));
}
static void pnv_core_realize(DeviceState *dev, Error **errp)
@@ -140,6 +155,14 @@ static void pnv_core_realize(DeviceState *dev, Error
**errp)
void *obj;
int i, j;
char name[32];
+ Object *xi;
+
+ xi = object_property_get_link(OBJECT(dev), "xics", &local_err);
+ if (!xi) {
+ error_setg(errp, "%s: required link 'xics' not found: %s",
+ __func__, error_get_pretty(local_err));
+ return;
+ }
pc->threads = g_malloc0(size * cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
@@ -160,7 +183,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
for (j = 0; j < cc->nr_threads; j++) {
obj = pc->threads + j * size;
- pnv_core_realize_child(obj, &local_err);
+ pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err);
if (local_err) {
goto err;
}
--
2.7.4
- [Qemu-devel] [PATCH v5 0/9] ppc/pnv: interrupt controller (POWER8), Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 1/9] spapr: move the IRQ server number mapping under the machine, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 2/9] spapr: allocate the ICPState object from under sPAPRCPUCore, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 3/9] ppc/xics: add a realize() handler to ICPStateClass, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 5/9] ppc/pnv: extend the machine with a XICSFabric interface, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 4/9] ppc/pnv: add a PnvICPState object, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 6/9] ppc/pnv: extend the machine with a InterruptStatsProvider interface, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 7/9] ppc/pnv: create the ICP object under PnvCore,
Cédric Le Goater <=
- [Qemu-devel] [PATCH v5 8/9] ppc/pnv: add a helper to calculate MMIO addresses registers, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 9/9] ppc/pnv: add memory regions for the ICP registers, Cédric Le Goater, 2017/04/03
- Re: [Qemu-devel] [PATCH v5 0/9] ppc/pnv: interrupt controller (POWER8), David Gibson, 2017/04/05