[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH] tcg/i386: Display AMD HT warning only for KVM
From: |
Eduardo Habkost |
Subject: |
Re: [Qemu-devel] [PATCH] tcg/i386: Display AMD HT warning only for KVM |
Date: |
Wed, 29 Mar 2017 08:58:12 -0300 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Wed, Mar 29, 2017 at 10:31:13AM +0200, Paolo Bonzini wrote:
> On 29/03/2017 06:32, Pranith Kumar wrote:
> > TCG uses the AMD cpu which warns when we use hyperthreading. Disable
> > the warning for TCG since it is not necessary.
> >
> > Signed-off-by: Pranith Kumar <address@hidden>
> > ---
> > target/i386/cpu.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 7aa762245a..66242893b6 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -3647,7 +3647,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
> > **errp)
> > * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
> > * cs->nr_threads hasn't be populated yet and the checking is
> > incorrect.
> > */
> > - if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
> > + if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned &&
> > kvm_enabled()) {
> > error_report("AMD CPU doesn't support hyperthreading. Please
> > configure"
> > " -smp options properly.");
> > ht_warned = true;
>
> AMD Zen supports hyperthreading. We should check if it uses the same
> CPUID leaves and drop the if completely (but not in 2.9).
AMD's CPUID specification documents the same bit
(CPUID[1].EDX[bit 28]) as "HTT: hyper-threading technology".
However:
* Their Extended Method for topology enumeration
ignores HTT and CmpLegacy, and has contiguous APIC IDs assigned
for each core[1]. I don't know if their Extended Method is
compatible[2] with the topology information we expose when
nr_threads>1. (I expect it to be compatible, but I'm not sure.)
* Their docs for the Legacy Method for CPU topology enumeration
don't mention what to do if CmpLegacy=0, HTT=1.
[1] The APIC ID formula is:
LocalApicId[proc=i, core=j] = (OFFSET_IDX + i) * MNC + j
[2] By compatible, I mean placing the cores/threads at the right
physical processor, at least (even if it treats each thread
as a separate core).
--
Eduardo