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[Qemu-devel] [PATCH v2 0/8] ppc/pnv: interrupt controller (POWER8)
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH v2 0/8] ppc/pnv: interrupt controller (POWER8) |
Date: |
Thu, 16 Mar 2017 15:35:04 +0100 |
Hello,
Here is a series adding support for the interrupt controller as found
on a POWER8 system. POWER9 uses a different interrupt controller
called XIVE, still to be worked on.
The initial patches are more cleanups of the XICS layer which move the
IRQ 'server' number mapping under the machine handlers. The PowerNV
machine is then extended with the Interrupt Source Control (ICS), the
Interrupt Control Presenter (ICP) objects and the Interrupt Management
area.
To test, grab a kernel and a rootfs image here :
https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/zImage.epapr
https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/rootfs.cpio.xz
The full patchset is available here :
https://github.com/legoater/qemu/commits/powernv-ipmi-2.9
Thanks,
C.
Changes since v1:
- introduced PnvICPState to hold the ICP memory region
- handled pir-to-cpu_index mapping under the machine icp_get handler
- added multichip support
- removed ics_eoi handler (came from a bug in PHB3_MSI)
- kept PSI and OCC model for later, when this part is done.
Cédric Le Goater (8):
ppc/xics: introduce an ICPState backlink under PowerPCCPU
spapr: move the IRQ server number mapping under the machine
ppc/xics: add a realize() handler to ICPStateClass
ppc/pnv: add a PnvICPState object
ppc/pnv: create the ICP and ICS objects under the machine
ppc/pnv: add a helper to calculate MMIO addresses registers
ppc/pnv: link the CPUs to the machine XICSFabric
ppc/pnv: add memory regions for the ICP registers
hw/intc/Makefile.objs | 1 +
hw/intc/xics.c | 9 ++-
hw/intc/xics_pnv.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++
hw/intc/xics_spapr.c | 25 ++-----
hw/ppc/pnv.c | 185 ++++++++++++++++++++++++++++++++++++++++++++++++
hw/ppc/pnv_core.c | 20 ++++--
hw/ppc/spapr.c | 3 +-
hw/ppc/spapr_cpu_core.c | 4 +-
include/hw/ppc/pnv.h | 35 ++++++++-
include/hw/ppc/xics.h | 14 ++++
target/ppc/cpu.h | 2 +
11 files changed, 451 insertions(+), 27 deletions(-)
create mode 100644 hw/intc/xics_pnv.c
--
2.7.4
- [Qemu-devel] [PATCH v2 0/8] ppc/pnv: interrupt controller (POWER8),
Cédric Le Goater <=
- [Qemu-devel] [PATCH v2 1/8] ppc/xics: introduce an ICPState backlink under PowerPCCPU, Cédric Le Goater, 2017/03/16
- [Qemu-devel] [PATCH v2 2/8] spapr: move the IRQ server number mapping under the machine, Cédric Le Goater, 2017/03/16
- [Qemu-devel] [PATCH v2 3/8] ppc/xics: add a realize() handler to ICPStateClass, Cédric Le Goater, 2017/03/16
- [Qemu-devel] [PATCH v2 4/8] ppc/pnv: add a PnvICPState object, Cédric Le Goater, 2017/03/16
- [Qemu-devel] [PATCH v2 5/8] ppc/pnv: create the ICP and ICS objects under the machine, Cédric Le Goater, 2017/03/16