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[Qemu-devel] [PULL 11/30] ARM i.MX timers: fix reset handling
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/30] ARM i.MX timers: fix reset handling |
Date: |
Mon, 27 Feb 2017 18:04:40 +0000 |
From: Kurban Mallachiev <address@hidden>
The i.MX timer device can be reset by writing to the SWR bit
of the CR register. This has to behave differently from hard
(power-on) reset because it does not reset all of the bits
in the CR register.
We were incorrectly implementing soft reset and hard reset
the same way, and in addition had a logic error which meant
that we were clearing the bits that soft-reset is supposed
to preserve and not touching the bits that soft-reset clears.
This was not correct behaviour for either kind of reset.
Separate out the soft reset and hard reset code paths, and
correct the handling of reset of the CR register so that it
is correct in both cases.
Signed-off-by: Kurban Mallachiev <address@hidden>
[PMM: rephrased commit message, spacing on operators;
use bool rather than int for is_soft_reset]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/timer/imx_gpt.c | 33 +++++++++++++++++++++++++--------
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index 010ccbf..4b9b54b 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -296,18 +296,23 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset,
unsigned size)
return reg_value;
}
-static void imx_gpt_reset(DeviceState *dev)
-{
- IMXGPTState *s = IMX_GPT(dev);
+static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset)
+{
/* stop timer */
ptimer_stop(s->timer);
- /*
- * Soft reset doesn't touch some bits; hard reset clears them
+ /* Soft reset and hard reset differ only in their handling of the CR
+ * register -- soft reset preserves the values of some bits there.
*/
- s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN|
- GPT_CR_WAITEN|GPT_CR_DBGEN);
+ if (is_soft_reset) {
+ /* Clear all CR bits except those that are preserved by soft reset. */
+ s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN |
+ GPT_CR_WAITEN | GPT_CR_DBGEN |
+ (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT);
+ } else {
+ s->cr = 0;
+ }
s->sr = 0;
s->pr = 0;
s->ir = 0;
@@ -333,6 +338,18 @@ static void imx_gpt_reset(DeviceState *dev)
}
}
+static void imx_gpt_soft_reset(DeviceState *dev)
+{
+ IMXGPTState *s = IMX_GPT(dev);
+ imx_gpt_reset_common(s, true);
+}
+
+static void imx_gpt_reset(DeviceState *dev)
+{
+ IMXGPTState *s = IMX_GPT(dev);
+ imx_gpt_reset_common(s, false);
+}
+
static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
@@ -348,7 +365,7 @@ static void imx_gpt_write(void *opaque, hwaddr offset,
uint64_t value,
s->cr = value & ~0x7c14;
if (s->cr & GPT_CR_SWR) { /* force reset */
/* handle the reset */
- imx_gpt_reset(DEVICE(s));
+ imx_gpt_soft_reset(DEVICE(s));
} else {
/* set our freq, as the source might have changed */
imx_gpt_set_freq(s);
--
2.7.4
- [Qemu-devel] [PULL 10/30] hw/arm/virt: Add a user option to disallow ITS instantiation, (continued)
- [Qemu-devel] [PULL 10/30] hw/arm/virt: Add a user option to disallow ITS instantiation, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 08/30] Add missing fp_access_check() to aarch64 crypto instructions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 07/30] hw/arm/virt: fix cpu object reference leak, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 25/30] bcm2835_sdhost: add bcm2835 sdhost controller, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 05/30] sd: sdhci: conditionally invoke multi block transfer, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 30/30] hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 02/30] bcm2835_rng: Use qcrypto_random_bytes() rather than rand(), Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 06/30] sd: sdhci: Remove block count enable check in single block transfers, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 13/30] armv7m: Implement reading and writing of PRIGROUP, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 11/30] ARM i.MX timers: fix reset handling,
Peter Maydell <=
- [Qemu-devel] [PULL 27/30] bcm2835_gpio: add bcm2835 gpio controller, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 04/30] sd: sdhci: check transfer mode register in multi block transfer, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 03/30] sd: sdhci: mask transfer mode register value, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 29/30] hw/arm/exynos: Fix Linux kernel division by zero for PLLs, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 09/30] cputlb: Don't assume do_unassigned_access() never returns, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 14/30] armv7m: Rewrite NVIC to not use any GIC code, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 28/30] bcm2835: add sdhost and gpio controllers, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 12/30] armv7m: Rename nvic_state to NVICState, Peter Maydell, 2017/02/27
- Re: [Qemu-devel] [PULL 00/30] target-arm queue, no-reply, 2017/02/27
- Re: [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2017/02/28