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[Qemu-devel] [PATCHv2 9/9] target/ppc: Correct SDR1 masking
From: |
David Gibson |
Subject: |
[Qemu-devel] [PATCHv2 9/9] target/ppc: Correct SDR1 masking |
Date: |
Mon, 27 Feb 2017 16:12:39 +1100 |
SDR_64_HTABORG, which indicates the bits of the SDR1 register to use for
the base of a 64-bit machine's hashed page table (HPT) isn't correct. It
includes the top 46 bits of the register, but in fact the top 4 bits must
be zero (according to the ISA v2.07). No actual implementation has
supported close to 2^60 bytes of physical address space, so it's kind of
irrelevant, but we might as well correct this.
In addition, although we checked for bad size values in SDR1, we never
reported an error if entirely invalid bits were set there. Add this check
to ppc_store_sdr1().
Reported-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/mmu-hash64.h | 2 +-
target/ppc/mmu_helper.c | 6 ++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 9c74823..54f1e37 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -56,7 +56,7 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
* Hash page table definitions
*/
-#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
+#define SDR_64_HTABORG 0x0FFFFFFFFFFC0000ULL
#define SDR_64_HTABSIZE 0x000000000000001FULL
#define HPTES_PER_GROUP 8
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 3bc8030..a1af3d6 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -2007,8 +2007,14 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
assert(!cpu->vhyp);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
+ target_ulong sdr_mask = SDR_64_HTABORG | SDR_64_HTABSIZE;
target_ulong htabsize = value & SDR_64_HTABSIZE;
+ if (value & ~sdr_mask) {
+ error_report("Invalid bits 0x"TARGET_FMT_lx" set in SDR1",
+ value & ~sdr_mask);
+ value &= sdr_mask;
+ }
if (htabsize > 28) {
error_report("Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1",
htabsize);
--
2.9.3
- [Qemu-devel] [PATCHv2 0/9] Cleanups to handling of hash MMU, David Gibson, 2017/02/27
- [Qemu-devel] [PATCHv2 4/9] target/ppc: SDR1 is a hypervisor resource, David Gibson, 2017/02/27
- [Qemu-devel] [PATCHv2 2/9] pseries: Minor cleanups to HPT management hypercalls, David Gibson, 2017/02/27
- [Qemu-devel] [PATCHv2 9/9] target/ppc: Correct SDR1 masking,
David Gibson <=
- [Qemu-devel] [PATCHv2 1/9] target/ppc: Fix KVM-HV HPTE accessors, David Gibson, 2017/02/27
- [Qemu-devel] [PATCHv2 3/9] target/ppc: Merge cpu_ppc_set_vhyp() with cpu_ppc_set_papr(), David Gibson, 2017/02/27
- [Qemu-devel] [PATCHv2 8/9] target/ppc: Remove the function ppc_hash64_set_sdr1(), David Gibson, 2017/02/27
- [Qemu-devel] [PATCHv2 7/9] target/ppc: Manage external HPT via virtual hypervisor, David Gibson, 2017/02/27
- [Qemu-devel] [PATCHv2 6/9] target/ppc: Eliminate htab_base and htab_mask variables, David Gibson, 2017/02/27
- [Qemu-devel] [PATCHv2 5/9] target/ppc: Cleanup HPTE accessors for 64-bit hash MMU, David Gibson, 2017/02/27