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[Qemu-devel] [PULL 13/24] cputlb: add assert_cpu_is_self checks
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PULL 13/24] cputlb: add assert_cpu_is_self checks |
Date: |
Fri, 24 Feb 2017 11:20:58 +0000 |
For SoftMMU the TLB flushes are an example of a task that can be
triggered on one vCPU by another. To deal with this properly we need to
use safe work to ensure these changes are done safely. The new assert
can be enabled while debugging to catch these cases.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
cputlb.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/cputlb.c b/cputlb.c
index 1cc9d9da51..af0e65cd2c 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -58,6 +58,12 @@
} \
} while (0)
+#define assert_cpu_is_self(this_cpu) do { \
+ if (DEBUG_TLB_GATE) { \
+ g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \
+ } \
+ } while (0)
+
/* statistics */
int tlb_flush_count;
@@ -70,6 +76,9 @@ void tlb_flush(CPUState *cpu)
{
CPUArchState *env = cpu->env_ptr;
+ assert_cpu_is_self(cpu);
+ tlb_debug("(count: %d)\n", tlb_flush_count++);
+
memset(env->tlb_table, -1, sizeof(env->tlb_table));
memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
@@ -77,13 +86,13 @@ void tlb_flush(CPUState *cpu)
env->vtlb_index = 0;
env->tlb_flush_addr = -1;
env->tlb_flush_mask = 0;
- tlb_flush_count++;
}
static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
{
CPUArchState *env = cpu->env_ptr;
+ assert_cpu_is_self(cpu);
tlb_debug("start\n");
for (;;) {
@@ -128,6 +137,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
int i;
int mmu_idx;
+ assert_cpu_is_self(cpu);
tlb_debug("page :" TARGET_FMT_lx "\n", addr);
/* Check if we need to flush due to large pages. */
@@ -165,6 +175,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong
addr, ...)
va_start(argp, addr);
+ assert_cpu_is_self(cpu);
tlb_debug("addr "TARGET_FMT_lx"\n", addr);
/* Check if we need to flush due to large pages. */
@@ -253,6 +264,8 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1,
ram_addr_t length)
int mmu_idx;
+ assert_cpu_is_self(cpu);
+
env = cpu->env_ptr;
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
unsigned int i;
@@ -284,6 +297,8 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
int i;
int mmu_idx;
+ assert_cpu_is_self(cpu);
+
vaddr &= TARGET_PAGE_MASK;
i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
@@ -343,6 +358,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong
vaddr,
unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;
int asidx = cpu_asidx_from_attrs(cpu, attrs);
+ assert_cpu_is_self(cpu);
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
tlb_add_large_page(env, vaddr, size);
--
2.11.0
- [Qemu-devel] [PULL 06/24] tcg: add kick timer for single-threaded vCPU emulation, (continued)
- [Qemu-devel] [PULL 06/24] tcg: add kick timer for single-threaded vCPU emulation, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 01/24] docs: new design document multi-thread-tcg.txt, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 05/24] tcg: add options for enabling MTTCG, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 07/24] tcg: rename tcg_current_cpu to tcg_current_rr_cpu, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 10/24] tcg: enable tb_lock() for SoftMMU, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 11/24] tcg: enable thread-per-vCPU, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 08/24] tcg: drop global lock during TCG code execution, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 09/24] tcg: remove global exit_request, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 12/24] tcg: handle EXCP_ATOMIC exception for system emulation, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 14/24] cputlb: tweak qemu_ram_addr_from_host_nofail reporting, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 13/24] cputlb: add assert_cpu_is_self checks,
Alex Bennée <=
- [Qemu-devel] [PULL 15/24] cputlb: introduce tlb_flush_* async work., Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 17/24] cputlb: add tlb_flush_by_mmuidx async routines, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 22/24] target-arm: ensure all cross vCPUs TLB flushes complete, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 18/24] cputlb: atomically update tlb fields used by tlb_reset_dirty, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 24/24] tcg: enable MTTCG by default for ARM on x86 hosts, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 23/24] hw/misc/imx6_src: defer clearing of SRC_SCR reset bits, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 20/24] target-arm/powerctl: defer cpu reset work to CPU context, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 16/24] cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap, Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 19/24] cputlb: introduce tlb_flush_*_all_cpus[_synced], Alex Bennée, 2017/02/24
- [Qemu-devel] [PULL 21/24] target-arm: don't generate WFE/YIELD calls for MTTCG, Alex Bennée, 2017/02/24