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Re: [Qemu-devel] [PATCH 1/2] aspeed/smc: add a 'sdram_base' property


From: Cédric Le Goater
Subject: Re: [Qemu-devel] [PATCH 1/2] aspeed/smc: add a 'sdram_base' property
Date: Mon, 20 Feb 2017 15:30:08 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0

On 02/20/2017 02:51 PM, Peter Maydell wrote:
> On 13 February 2017 at 14:44, Cédric Le Goater <address@hidden> wrote:
>> The setting of the DRAM address of the DMA transaction depends on the
>> DRAM base address of the SoC. Let's add a property to give this
>> information to the SMC controller model.
>>
>> Signed-off-by: Cédric Le Goater <address@hidden>
>> Reviewed-by: Joel Stanley <address@hidden>
>> Reviewed-by: Andrew Jeffery <address@hidden>
>> --
> 
> This seems a bit weird -- what does it actually do in hardware?
> (Does it really have the ability to dma anywhere in the
> address space and just use an odd base address, or is it
> DMA'ing to a more restricted address space?)

For the AST2500, the valid address range for the DRAM side start
address of the DMA is [ 0x80000000 - 0xBFFFFFFF ] which is the 
full 1024M SDRAM space. It will wrap back in case of overflow.

For the AST2400, it is [ 0x40000000 - 0x5FFFFFFF ] which is the 
full 512M SDRAM space.

And the length of the DMA goes from 4 bytes to 32MB [ O - 0x7FFFFF ]

On real HW, the DRAM address of the DMA is taken as an offset from 
the beginning of the SDRAM address space. It does the same for 
the flash address btw. This is why we have the macros in the model : 

#define DMA_DRAM_ADDR(base, x)  (((x) & ~0xE0000003) | base)
#define DMA_FLASH_ADDR(x)       (((x) & ~0xE0000003) | \
                                 ASPEED_SOC_FMC_FLASH_BASE)


Thanks,

C.



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