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Re: [Qemu-devel] [PATCH v4 1/4] sd: sdhci: mask transfer mode register v
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v4 1/4] sd: sdhci: mask transfer mode register value |
Date: |
Tue, 14 Feb 2017 11:12:16 -0800 |
On Tue, Feb 14, 2017 at 10:52 AM, P J P <address@hidden> wrote:
> From: Prasad J Pandit <address@hidden>
>
> In SDHCI protocol, the transfer mode register is defined
> to be of 6 bits. Mask its value with '0x0037' so that an
> invalid value could not be assigned.
>
> Signed-off-by: Prasad J Pandit <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Thanks,
Alistair
> ---
> hw/sd/sdhci.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> Update per: use macro for the mask value
> -> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg02774.html
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 5bd5ab6..cf647fa 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -119,6 +119,7 @@
> (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
> (SDHC_CAPAB_TOCLKFREQ))
>
> +#define MASK_TRNMOD 0x0037
> #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
>
> static uint8_t sdhci_slotint(SDHCIState *s)
> @@ -1050,7 +1051,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
> unsigned size)
> if (!(s->capareg & SDHC_CAN_DO_DMA)) {
> value &= ~SDHC_TRNS_DMA;
> }
> - MASKED_WRITE(s->trnmod, mask, value);
> + MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD);
> MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
>
> /* Writing to the upper byte of CMDREG triggers SD command
> generation */
> --
> 2.9.3
[Qemu-devel] [PATCH v4 3/4] sd: sdhci: conditionally invoke multi block transfer, P J P, 2017/02/14
[Qemu-devel] [PATCH v4 4/4] sd: sdhci: Remove block count enable check in single block transfers, P J P, 2017/02/14
Re: [Qemu-devel] [PATCH v4 0/4] sd: sdhci: correct transfer mode register usage, Peter Maydell, 2017/02/17