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[Qemu-devel] [PATCH 09/22] target/openrisc: Put SR[OVE] in TB flags
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 09/22] target/openrisc: Put SR[OVE] in TB flags |
Date: |
Wed, 8 Feb 2017 20:51:41 -0800 |
Removes a call at execution time for overflow exceptions.
Signed-off-by: Richard Henderson <address@hidden>
---
target/openrisc/cpu.h | 4 ++--
target/openrisc/exception_helper.c | 2 +-
target/openrisc/translate.c | 24 +++++++++++++++---------
3 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 06d0e89..ef90e49 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -400,8 +400,8 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState
*env,
{
*pc = env->pc;
*cs_base = 0;
- /* D_FLAG -- branch instruction exception */
- *flags = (env->flags & D_FLAG);
+ /* D_FLAG -- branch instruction exception, OVE overflow trap enable. */
+ *flags = (env->flags & D_FLAG) | (env->sr & SR_OVE);
}
static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
diff --git a/target/openrisc/exception_helper.c
b/target/openrisc/exception_helper.c
index 7e54c97..5147da6 100644
--- a/target/openrisc/exception_helper.c
+++ b/target/openrisc/exception_helper.c
@@ -32,7 +32,7 @@ void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp)
void HELPER(ove)(CPUOpenRISCState *env, target_ulong test)
{
- if (unlikely(test) && (env->sr & SR_OVE)) {
+ if (unlikely(test)) {
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 7c6cd1c..b8116ba 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -132,8 +132,8 @@ static inline void wb_SR_F(void)
static inline void gen_sync_flags(DisasContext *dc)
{
/* Sync the tb dependent flag between translate and runtime. */
- if (dc->tb_flags != dc->synced_flags) {
- tcg_gen_movi_tl(env_flags, dc->tb_flags);
+ if ((dc->tb_flags ^ dc->synced_flags) & D_FLAG) {
+ tcg_gen_movi_tl(env_flags, dc->tb_flags & D_FLAG);
dc->synced_flags = dc->tb_flags;
}
}
@@ -249,20 +249,26 @@ static void gen_jump(DisasContext *dc, int32_t n26,
uint32_t reg, uint32_t op0)
static void gen_ove_cy(DisasContext *dc, TCGv cy)
{
- gen_helper_ove(cpu_env, cy);
+ if (dc->tb_flags & SR_OVE) {
+ gen_helper_ove(cpu_env, cy);
+ }
}
static void gen_ove_ov(DisasContext *dc, TCGv ov)
{
- gen_helper_ove(cpu_env, ov);
+ if (dc->tb_flags & SR_OVE) {
+ gen_helper_ove(cpu_env, ov);
+ }
}
static void gen_ove_cyov(DisasContext *dc, TCGv cy, TCGv ov)
{
- TCGv t0 = tcg_temp_new();
- tcg_gen_or_tl(t0, cy, ov);
- gen_helper_ove(cpu_env, t0);
- tcg_temp_free(t0);
+ if (dc->tb_flags & SR_OVE) {
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_or_tl(t0, cy, ov);
+ gen_helper_ove(cpu_env, t0);
+ tcg_temp_free(t0);
+ }
}
static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
@@ -1606,7 +1612,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct
TranslationBlock *tb)
dc->flags = cpu->env.cpucfgr;
dc->mem_idx = cpu_mmu_index(&cpu->env, false);
dc->synced_flags = dc->tb_flags = tb->flags;
- dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
+ dc->delayed_branch = (dc->tb_flags & D_FLAG) != 0;
dc->singlestep_enabled = cs->singlestep_enabled;
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
--
2.9.3
- [Qemu-devel] [PATCH 00/22] target/openrisc updates, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 01/22] target/openrisc: Rename the cpu from or32 to or1k, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 03/22] linux-user: Fix openrisc cpu_loop, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 04/22] target/openrisc: Fix exception handling status registers, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 05/22] target/openrisc: Implement lwa, swa, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 06/22] target/openrisc: Tidy insn dumping, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 07/22] target/openrisc: Rationalize immediate extraction, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 08/22] target/openrisc: Streamline arithmetic and OVE, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 09/22] target/openrisc: Put SR[OVE] in TB flags,
Richard Henderson <=
- [Qemu-devel] [PATCH 10/22] target/openrisc: Invert the decoding in dec_calc, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 12/22] target/openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 13/22] target/openrisc: Use movcond where appropriate, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 14/22] target/openrisc: Set flags on helpers, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 11/22] target/openrisc: Keep SR_F in a separate variable, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 15/22] target/openrisc: Enable trap, csync, msync, psync for user mode, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 16/22] target/openrisc: Implement msync, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 17/22] target/openrisc: Represent MACHI:MACLO as a single unit, Richard Henderson, 2017/02/08