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[Qemu-devel] [PULL 16/22] armv7m: Honour CCR.USERSETMPEND
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 16/22] armv7m: Honour CCR.USERSETMPEND |
Date: |
Fri, 27 Jan 2017 15:32:11 +0000 |
From: Michael Davidsaver <address@hidden>
The CCR.USERSETMPEND bit has to be set to permit unprivileged code to
write to the Software Triggered Interrupt register; honour this bit
rather than letting any code write to the register.
Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: Tweak commit message, comment, phrasing of condition]
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/armv7m_nvic.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 60e72d7..fe5c303 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -409,7 +409,10 @@ static void nvic_writel(nvic_state *s, uint32_t offset,
uint32_t value)
"NVIC: Aux fault status registers unimplemented\n");
break;
case 0xf00: /* Software Triggered Interrupt Register */
- if ((value & 0x1ff) < s->num_irq) {
+ /* user mode can only write to STIR if CCR.USERSETMPEND permits it */
+ if ((value & 0x1ff) < s->num_irq &&
+ (arm_current_el(&cpu->env) ||
+ (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) {
gic_set_pending_private(&s->gic, 0, value & 0x1ff);
}
break;
--
2.7.4
- [Qemu-devel] [PULL 00/22] target-arm queue, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 21/22] arm_gicv3: Fix broken logic in ELRSR calculation, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 20/22] hw/char/exynos4210_uart: Drop unused local variable frame_size, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 22/22] dma: omap: check dma channel data_type, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 18/22] armv7m: R14 should reset to 0xffffffff, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 19/22] arm: stellaris: make MII accesses complete immediately, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 17/22] armv7m: FAULTMASK should be 0 on reset, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 14/22] armv7m: set CFSR.UNDEFINSTR on undefined instructions, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 13/22] armv7m: honour CCR.STACKALIGN on exception entry, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 09/22] target/arm: Drop IS_M() macro, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 16/22] armv7m: Honour CCR.USERSETMPEND,
Peter Maydell <=
- [Qemu-devel] [PULL 05/22] hw/registerfields.h: Pull FIELD etc macros out of hw/register.h, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 07/22] armv7m: Clear FAULTMASK on return from non-NMI exceptions, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 01/22] aspeed/smc: handle dummy bytes when doing fast reads in command mode, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 02/22] armv7m: MRS/MSR: handle unprivileged access, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 12/22] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 06/22] armv7m: Fix reads of CONTROL register bit 1, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 04/22] armv7m: Explicit error for bad vector table, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 11/22] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 10/22] armv7m_nvic: keep a pointer to the CPU, Peter Maydell, 2017/01/27
- [Qemu-devel] [PULL 08/22] pflash_cfi01: fix per-device sector length in CFI table, Peter Maydell, 2017/01/27