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[Qemu-devel] [PULL 16/22] armv7m: Honour CCR.USERSETMPEND


From: Peter Maydell
Subject: [Qemu-devel] [PULL 16/22] armv7m: Honour CCR.USERSETMPEND
Date: Fri, 27 Jan 2017 15:32:11 +0000

From: Michael Davidsaver <address@hidden>

The CCR.USERSETMPEND bit has to be set to permit unprivileged code to
write to the Software Triggered Interrupt register; honour this bit
rather than letting any code write to the register.

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: Tweak commit message, comment, phrasing of condition]
Signed-off-by: Peter Maydell <address@hidden>
---
 hw/intc/armv7m_nvic.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 60e72d7..fe5c303 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -409,7 +409,10 @@ static void nvic_writel(nvic_state *s, uint32_t offset, 
uint32_t value)
                       "NVIC: Aux fault status registers unimplemented\n");
         break;
     case 0xf00: /* Software Triggered Interrupt Register */
-        if ((value & 0x1ff) < s->num_irq) {
+        /* user mode can only write to STIR if CCR.USERSETMPEND permits it */
+        if ((value & 0x1ff) < s->num_irq &&
+            (arm_current_el(&cpu->env) ||
+             (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) {
             gic_set_pending_private(&s->gic, 0, value & 0x1ff);
         }
         break;
-- 
2.7.4




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