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[Qemu-devel] [PULL 08/36] aspeed/smc: remove call to aspeed_smc_update_c
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/36] aspeed/smc: remove call to aspeed_smc_update_cs() in reset function |
Date: |
Thu, 19 Jan 2017 14:09:27 +0000 |
From: Cédric Le Goater <address@hidden>
Instead, we can simply set the irq level when unselecting the slave
devices. This change prepares ground for a subsequent cleanup of the
aspeed_smc_update_cs() routine which uselessly loops on all slaves to
update their status.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/ssi/aspeed_smc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 8a7217d..205c0ab 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -424,6 +424,7 @@ static void aspeed_smc_reset(DeviceState *d)
/* Unselect all slaves */
for (i = 0; i < s->num_cs; ++i) {
s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
+ qemu_set_irq(s->cs_lines[i], true);
}
/* setup default segment register values for all */
@@ -431,8 +432,6 @@ static void aspeed_smc_reset(DeviceState *d)
s->regs[R_SEG_ADDR0 + i] =
aspeed_smc_segment_to_reg(&s->ctrl->segments[i]);
}
-
- aspeed_smc_update_cs(s);
}
static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
--
2.7.4
- [Qemu-devel] [PULL 21/36] target-arm: Expose output GPIO line for VCPU maintenance interrupt, (continued)
- [Qemu-devel] [PULL 21/36] target-arm: Expose output GPIO line for VCPU maintenance interrupt, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 22/36] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 28/36] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 24/36] hw/intc/gicv3: Add defines for ICH system register fields, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 23/36] target-arm: Add ARMCPU fields for GIC CPU i/f config, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 31/36] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 27/36] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 33/36] hw/arm/virt-acpi-build: use SMC if booting in EL2, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 34/36] target/arm/psci.c: If EL2 implemented, start CPUs in EL2, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 32/36] hw/arm/virt: Support using SMC for PSCI, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 08/36] aspeed/smc: remove call to aspeed_smc_update_cs() in reset function,
Peter Maydell <=
- [Qemu-devel] [PULL 29/36] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 20/36] hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 25/36] hw/intc/gicv3: Add data fields for virtualization support, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 19/36] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 26/36] hw/intc/arm_gicv3: Add accessors for ICH_ system registers, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 30/36] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update(), Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 18/36] hw/arm/virt-acpi - reserve ECAM space as PNP0C02 device, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 15/36] aspeed/smc: extend tests for Command mode, Peter Maydell, 2017/01/19