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[Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrup
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode |
Date: |
Wed, 18 Jan 2017 23:38:19 +0100 |
As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005,
outstanding disrupting exceptions that are destined for privileged mode can only
cause a trap when the virtual processor is in nonprivileged or privileged mode
and
PSTATE.ie = 1. At all other times, they are held pending.
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/sparc/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index f65d8b5..21fe0d1 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -736,8 +736,9 @@ static inline int cpu_interrupts_enabled(CPUSPARCState
*env1)
if (env1->psret != 0)
return 1;
#else
- if (env1->pstate & PS_IE)
+ if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) {
return 1;
+ }
#endif
return 0;
--
2.7.2
- [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, (continued)
- [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, Richard Henderson, 2017/01/11
- Re: [Qemu-devel] [PULL 00/30] target-sparc sun4v support, no-reply, 2017/01/11
- Re: [Qemu-devel] [PULL 00/30] target-sparc sun4v support, Peter Maydell, 2017/01/13
- [Qemu-devel] [PULL 00/30] target-sparc sun4v support, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 02/30] target-sparc: store cpu super- and hypervisor flags in TB, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 03/30] target-sparc: use explicit mmu register pointers, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode,
Artyom Tarasenko <=
- [Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2017/01/18