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[Qemu-devel] [PULL v2 6/9] target-m68k: fix gen_flush_flags()
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PULL v2 6/9] target-m68k: fix gen_flush_flags() |
Date: |
Sat, 14 Jan 2017 10:07:55 +0100 |
gen_flush_flags() is setting unconditionally cc_op_synced to 1
and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set
to something else by a previous tcg fragment.
We fix that by not setting cc_op_synced to 1
(except for gen_helper_flush_flags() that updates env->cc_op)
FIX: https://github.com/vivier/qemu-m68k/issues/19
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
---
target/m68k/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 410f56a..0e97900 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -595,18 +595,19 @@ static void gen_flush_flags(DisasContext *s)
case CC_OP_DYNAMIC:
gen_helper_flush_flags(cpu_env, QREG_CC_OP);
+ s->cc_op_synced = 1;
break;
default:
t0 = tcg_const_i32(s->cc_op);
gen_helper_flush_flags(cpu_env, t0);
tcg_temp_free(t0);
+ s->cc_op_synced = 1;
break;
}
/* Note that flush_flags also assigned to env->cc_op. */
s->cc_op = CC_OP_FLAGS;
- s->cc_op_synced = 1;
}
static inline TCGv gen_extend(TCGv val, int opsize, int sign)
--
2.7.4
- [Qemu-devel] [PULL v2 0/9] M68k for 2.9 patches, Laurent Vivier, 2017/01/14
- [Qemu-devel] [PULL v2 7/9] target-m68k: manage pre-dec et post-inc in CAS, Laurent Vivier, 2017/01/14
- [Qemu-devel] [PULL v2 5/9] target-m68k: fix bit operation with immediate value, Laurent Vivier, 2017/01/14
- [Qemu-devel] [PULL v2 6/9] target-m68k: fix gen_flush_flags(),
Laurent Vivier <=
- [Qemu-devel] [PULL v2 8/9] target-m68k: CAS doesn't need aligned access, Laurent Vivier, 2017/01/14
- [Qemu-devel] [PULL v2 4/9] m68k: Remove PCI and USB from config file, Laurent Vivier, 2017/01/14
- [Qemu-devel] [PULL v2 2/9] target-m68k: Implement bitfield ops for memory, Laurent Vivier, 2017/01/14
- [Qemu-devel] [PULL v2 9/9] target-m68k: increment/decrement with SP, Laurent Vivier, 2017/01/14
- [Qemu-devel] [PULL v2 1/9] target-m68k: Implement bitfield ops for registers, Laurent Vivier, 2017/01/14
- [Qemu-devel] [PULL v2 3/9] target-m68k: Implement bfffo, Laurent Vivier, 2017/01/14
- Re: [Qemu-devel] [PULL v2 0/9] M68k for 2.9 patches, Peter Maydell, 2017/01/17