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Re: [Qemu-devel] [PATCH v2 1/5] target-m68k: fix bit operation with imme
From: |
Laurent Vivier |
Subject: |
Re: [Qemu-devel] [PATCH v2 1/5] target-m68k: fix bit operation with immediate value |
Date: |
Fri, 13 Jan 2017 19:23:41 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 |
Le 13/01/2017 à 18:55, Richard Henderson a écrit :
> On 01/13/2017 04:51 AM, Laurent Vivier wrote:
>> M680x0 bit operations with an immediate value use 9 bits of the 16bit
>> value, while coldfire ones use only 8 bits.
>
> I don't see that in the reference manual. Where do you get this from?
See "BSET Instruction Format:BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE
DATA", p. 4.58 of "M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL", "BIT
NUMBER" is bits 0 to 8 of extended word.
See "Test a Bit and Set", p. 4-22 of "ColdFire Family Programmer’s
Reference Manual, Rev. 3" (link given by Thomas), "Bit Number" is bits 0
to 7 of extended word.
I've found the problem with RISU.
Thanks,
Laurent
- [Qemu-devel] [PATCH v2 0/5] Fixes for target/m68k, Laurent Vivier, 2017/01/13
- [Qemu-devel] [PATCH v2 2/5] target-m68k: fix gen_flush_flags(), Laurent Vivier, 2017/01/13
- [Qemu-devel] [PATCH v2 4/5] target-m68k: CAS doesn't need aligned access, Laurent Vivier, 2017/01/13
- [Qemu-devel] [PATCH v2 5/5] target-m68k: increment/decrement with SP, Laurent Vivier, 2017/01/13
- [Qemu-devel] [PATCH v2 3/5] target-m68k: manage pre-dec et post-inc in CAS, Laurent Vivier, 2017/01/13