[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 17/30] target-sparc: ignore writes to UA2005 CPU
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v2 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register |
Date: |
Wed, 11 Jan 2017 21:19:48 +0100 |
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/sparc/ldst_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 301616b..d524aaa 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1629,6 +1629,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr,
target_ulong val,
env->scratch[i] = val;
return;
}
+ case ASI_QUEUE: /* UA2005 CPU mondo queue */
case ASI_DCACHE_DATA: /* D-cache data */
case ASI_DCACHE_TAG: /* D-cache tag access */
case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
--
1.8.3.1
- [Qemu-devel] [PATCH v2 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, (continued)
- [Qemu-devel] [PATCH v2 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 15/30] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v2 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 18/30] target-sparc: replace the last tlb entry when no free entries left, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 21/30] target-sparc: simplify ultrasparc_tsb_pointer, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 20/30] target-sparc: implement UA2005 TSB Pointers, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 22/30] target-sparc: allow 256M sized pages, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 23/30] target-sparc: implement auto-demapping for UA2005 CPUs, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 24/30] target-sparc: add more registers to dump_mmu, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 25/30] target-sparc: implement UA2005 ASI_MMU (0x21), Artyom Tarasenko, 2017/01/11