[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 02/30] target-sparc: store cpu super- and hypervi
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v2 02/30] target-sparc: store cpu super- and hypervisor flags in TB |
Date: |
Wed, 11 Jan 2017 21:19:33 +0100 |
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target/sparc/cpu.h | 17 +++++++++++++++++
target/sparc/translate.c | 24 +++++++++++++++++++-----
2 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index e0b2806..68e39bc 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -667,6 +667,11 @@ static inline int cpu_supervisor_mode(CPUSPARCState *env1)
{
return env1->pstate & PS_PRIV;
}
+#else
+static inline int cpu_supervisor_mode(CPUSPARCState *env1)
+{
+ return env1->psrs;
+}
#endif
static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
@@ -733,6 +738,8 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
#define TB_FLAG_MMU_MASK 7
#define TB_FLAG_FPU_ENABLED (1 << 4)
#define TB_FLAG_AM_ENABLED (1 << 5)
+#define TB_FLAG_SUPER (1 << 6)
+#define TB_FLAG_HYPER (1 << 7)
#define TB_FLAG_ASI_SHIFT 24
static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
@@ -742,7 +749,17 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState
*env, target_ulong *pc,
*pc = env->pc;
*cs_base = env->npc;
flags = cpu_mmu_index(env, false);
+#ifndef CONFIG_USER_ONLY
+ if (cpu_supervisor_mode(env)) {
+ flags |= TB_FLAG_SUPER;
+ }
+#endif
#ifdef TARGET_SPARC64
+#ifndef CONFIG_USER_ONLY
+ if (cpu_hypervisor_mode(env)) {
+ flags |= TB_FLAG_HYPER;
+ }
+#endif
if (env->pstate & PS_AM) {
flags |= TB_FLAG_AM_ENABLED;
}
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 2205f89..0b0cde1 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -72,9 +72,16 @@ typedef struct DisasContext {
target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
int is_br;
int mem_idx;
- int fpu_enabled;
- int address_mask_32bit;
- int singlestep;
+ bool fpu_enabled;
+ bool address_mask_32bit;
+ bool singlestep;
+#ifndef CONFIG_USER_ONLY
+ bool supervisor;
+#ifdef TARGET_SPARC64
+ bool hypervisor;
+#endif
+#endif
+
uint32_t cc_op; /* current CC operation */
struct TranslationBlock *tb;
sparc_def_t *def;
@@ -283,10 +290,11 @@ static void gen_move_Q(DisasContext *dc, unsigned int rd,
unsigned int rs)
#define hypervisor(dc) 0
#endif
#else
-#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
#ifdef TARGET_SPARC64
-#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
+#define hypervisor(dc) (dc->hypervisor)
+#define supervisor(dc) (dc->supervisor | dc->hypervisor)
#else
+#define supervisor(dc) (dc->supervisor)
#endif
#endif
@@ -5710,9 +5718,15 @@ void gen_intermediate_code(CPUSPARCState * env,
TranslationBlock * tb)
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
dc->singlestep = (cs->singlestep_enabled || singlestep);
+#ifndef CONFIG_USER_ONLY
+ dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
+#endif
#ifdef TARGET_SPARC64
dc->fprs_dirty = 0;
dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
+#ifndef CONFIG_USER_ONLY
+ dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0;
+#endif
#endif
num_insns = 0;
--
1.8.3.1
- [Qemu-devel] [PATCH v2 00/30] target-sparc: add niagara OpenSPARC T1 sun4v emulation, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 02/30] target-sparc: store cpu super- and hypervisor flags in TB,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v2 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 04/30] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 03/30] target-sparc: use explicit mmu register pointers, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2017/01/11