From 3f946c9cebc4b5aec9bf4b7b081cf5ab017ba6c7 Mon Sep 17 00:00:00 2001 From: klemens Date: Sun, 25 Dec 2016 21:51:18 +0100 Subject: [PATCH 1/2] spelling fixes, just text, comments. --- Changelog | 2 +- aio-posix.c | 2 +- block/gluster.c | 2 +- block/vhdx.c | 2 +- disas/libvixl/vixl/a64/decoder-a64.h | 2 +- disas/libvixl/vixl/globals.h | 2 +- docs/COLO-FT.txt | 2 +- docs/multiseat.txt | 2 +- docs/qcow2-cache.txt | 2 +- docs/rdma.txt | 2 +- docs/specs/ppc-spapr-hotplug.txt | 2 +- include/elf.h | 2 +- include/exec/memory.h | 2 +- include/hw/arm/exynos4210.h | 2 +- include/hw/arm/omap.h | 2 +- include/hw/dma/xlnx_dpdma.h | 2 +- include/hw/pci-host/q35.h | 2 +- include/hw/pci/pcie_aer.h | 2 +- include/hw/register.h | 2 +- include/io/task.h | 2 +- include/qemu/qht.h | 2 +- include/qom/cpu.h | 4 ++-- include/sysemu/char.h | 4 ++-- include/sysemu/cryptodev.h | 2 +- ioport.c | 2 +- linux-user/syscall.c | 2 +- net/checksum.c | 4 ++-- net/filter.c | 2 +- qapi-schema.json | 2 +- scripts/clean-header-guards.pl | 2 +- target/arm/cpu.h | 4 ++-- target/arm/helper.c | 2 +- target/arm/translate-a64.c | 2 +- target/cris/helper.c | 6 +++--- target/cris/translate.c | 4 ++-- target/ppc/STATUS | 2 +- target/ppc/cpu.h | 2 +- target/ppc/excp_helper.c | 4 ++-- target/ppc/mmu-hash64.c | 4 ++-- target/ppc/mmu_helper.c | 2 +- target/s390x/cpu_models.h | 4 ++-- target/s390x/insn-data.def | 2 +- target/s390x/translate.c | 6 +++--- target/sh4/cpu.h | 2 +- target/tricore/helper.c | 2 +- tcg/aarch64/tcg-target.inc.c | 2 +- tests/ahci-test.c | 2 +- tests/bios-tables-test.c | 2 +- tests/migration/guestperf-batch.py | 2 +- tests/migration/guestperf.py | 2 +- tests/postcopy-test.c | 2 +- tests/test-throttle.c | 2 +- trace-events | 2 +- util/qemu-progress.c | 4 ++-- util/qemu-sockets.c | 2 +- util/qemu-thread-win32.c | 2 +- util/qht.c | 2 +- util/uri.c | 2 +- 58 files changed, 71 insertions(+), 71 deletions(-) diff --git a/Changelog b/Changelog index 1249b8a..ef38a44 100644 --- a/Changelog +++ b/Changelog @@ -241,7 +241,7 @@ version 0.8.0: version 0.7.2: - x86_64 fixes (Win2000 and Linux 2.6 boot in 32 bit) - - merge self modifying code handling in dirty ram page mecanism. + - merge self modifying code handling in dirty ram page mechanism. - MIPS fixes (Ralf Baechle) - better user net performances diff --git a/aio-posix.c b/aio-posix.c index e13b9ab..b2c1987 100644 --- a/aio-posix.c +++ b/aio-posix.c @@ -35,7 +35,7 @@ struct AioHandler #ifdef CONFIG_EPOLL_CREATE1 -/* The fd number threashold to switch to epoll */ +/* The fd number threshold to switch to epoll */ #define EPOLL_ENABLE_THRESHOLD 64 static void aio_epoll_disable(AioContext *ctx) diff --git a/block/gluster.c b/block/gluster.c index a0a74e4..35c223b 100644 --- a/block/gluster.c +++ b/block/gluster.c @@ -1253,7 +1253,7 @@ static int qemu_gluster_has_zero_init(BlockDriverState *bs) * If @start is in a trailing hole or beyond EOF, return -ENXIO. * If we can't find out, return a negative errno other than -ENXIO. * - * (Shamefully copied from raw-posix.c, only miniscule adaptions.) + * (Shamefully copied from raw-posix.c, only minuscule adaptions.) */ static int find_allocation(BlockDriverState *bs, off_t start, off_t *data, off_t *hole) diff --git a/block/vhdx.c b/block/vhdx.c index 0ba2f0a..a11b885 100644 --- a/block/vhdx.c +++ b/block/vhdx.c @@ -179,7 +179,7 @@ uint32_t vhdx_checksum_calc(uint32_t crc, uint8_t *buf, size_t size, /* Validates the checksum of the buffer, with an in-place CRC. * * Zero is substituted during crc calculation for the original crc field, - * and the crc field is restored afterwards. But the buffer will be modifed + * and the crc field is restored afterwards. But the buffer will be modified * during the calculation, so this may not be not suitable for multi-threaded * use. * diff --git a/disas/libvixl/vixl/a64/decoder-a64.h b/disas/libvixl/vixl/a64/decoder-a64.h index b3f04f6..045e2a7 100644 --- a/disas/libvixl/vixl/a64/decoder-a64.h +++ b/disas/libvixl/vixl/a64/decoder-a64.h @@ -215,7 +215,7 @@ class Decoder { // On entry, instruction bits 27:24 = 0x0. void DecodePCRelAddressing(const Instruction* instr); - // Decode the add/subtract immediate instruction, and call the correspoding + // Decode the add/subtract immediate instruction, and call the corresponding // visitors. // On entry, instruction bits 27:24 = 0x1. void DecodeAddSubImmediate(const Instruction* instr); diff --git a/disas/libvixl/vixl/globals.h b/disas/libvixl/vixl/globals.h index 61dc9f7..9ae6f7a 100644 --- a/disas/libvixl/vixl/globals.h +++ b/disas/libvixl/vixl/globals.h @@ -77,7 +77,7 @@ const int MBytes = 1024 * KBytes; #endif // This is not as powerful as template based assertions, but it is simple. // It assumes that the descriptions are unique. If this starts being a problem, -// we can switch to a different implemention. +// we can switch to a different implementation. #define VIXL_CONCAT(a, b) a##b #define VIXL_STATIC_ASSERT_LINE(line, condition) \ typedef char VIXL_CONCAT(STATIC_ASSERT_LINE_, line)[(condition) ? 1 : -1] \ diff --git a/docs/COLO-FT.txt b/docs/COLO-FT.txt index e289be2..bb05c3c 100644 --- a/docs/COLO-FT.txt +++ b/docs/COLO-FT.txt @@ -104,7 +104,7 @@ Primary side. COLO Proxy: Delivers packets to Primary and Seconday, and then compare the responses from both side. Then decide whether to start a checkpoint according to some rules. -Please refer to docs/colo-proxy.txt for more informations. +Please refer to docs/colo-proxy.txt for more information. Note: HeartBeat has not been implemented yet, so you need to trigger failover process diff --git a/docs/multiseat.txt b/docs/multiseat.txt index 807518c..fb7e790 100644 --- a/docs/multiseat.txt +++ b/docs/multiseat.txt @@ -62,7 +62,7 @@ to its own window so you can see both display devices side-by-side. For vnc some additional configuration on the command line is needed. We'll create two vnc server instances, and bind the second one to the -second seat, simliar to input devices: +second seat, similar to input devices: -display vnc=:1,id=primary \ -display vnc=:2,id=secondary,display=video.2 diff --git a/docs/qcow2-cache.txt b/docs/qcow2-cache.txt index 1fdd6f9..ef03390 100644 --- a/docs/qcow2-cache.txt +++ b/docs/qcow2-cache.txt @@ -55,7 +55,7 @@ value can improve the I/O performance significantly. The refcount blocks ------------------- -The qcow2 format also mantains a reference count for each cluster. +The qcow2 format also maintains a reference count for each cluster. Reference counts are used for cluster allocation and internal snapshots. The data is stored in a two-level structure similar to the L1/L2 tables described above. diff --git a/docs/rdma.txt b/docs/rdma.txt index 2bdd0a5..7a78314 100644 --- a/docs/rdma.txt +++ b/docs/rdma.txt @@ -261,7 +261,7 @@ qemu_rdma_exchange_send(header, data, optional response header & data): of the connection (described below). All of the remaining command types (not including 'ready') -described above all use the aformentioned two functions to do the hard work: +described above all use the aforementioned two functions to do the hard work: 1. After connection setup, RAMBlock information is exchanged using this protocol before the actual migration begins. This information includes diff --git a/docs/specs/ppc-spapr-hotplug.txt b/docs/specs/ppc-spapr-hotplug.txt index f57e2a0..6f3f45f 100644 --- a/docs/specs/ppc-spapr-hotplug.txt +++ b/docs/specs/ppc-spapr-hotplug.txt @@ -371,7 +371,7 @@ ibm,dynamic-memory This property describes the dynamically reconfigurable memory. It is a property encoded array that has an integer N, the number of LMBs followed -by N LMB list entires. +by N LMB list entries. Each LMB list entry consists of the following elements: diff --git a/include/elf.h b/include/elf.h index 1c2975d..fb9541b 100644 --- a/include/elf.h +++ b/include/elf.h @@ -987,7 +987,7 @@ typedef struct { #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ -/* Additional section indeces. */ +/* Additional section indices. */ #define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared symbols in ANSI C. */ diff --git a/include/exec/memory.h b/include/exec/memory.h index 64560f6..495ba84 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -386,7 +386,7 @@ void memory_region_init_ram(MemoryRegion *mr, Error **errp); /** - * memory_region_init_resizeable_ram: Initialize memory region with resizeable + * memory_region_init_resizeable_ram: Initialize memory region with resizable * RAM. Accesses into the region will * modify memory directly. Only an initial * portion of this RAM is actually used. diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 76bb6d4..6ac4c89 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -110,7 +110,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); /* Initialize board IRQs. - * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ + * These IRQs contain split Int/External Combiner and External Gic IRQs */ void exynos4210_init_board_irqs(Exynos4210Irq *s); /* Get IRQ number from exynos4210 IRQ subsystem stub. diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index f25870b..7b1c2d0 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -966,7 +966,7 @@ void omap_mpu_wakeup(void *opaque, int irq, int req); __FUNCTION__, paddr) /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area - (Board-specifc tags are not here) */ + (Board-specific tags are not here) */ #define OMAP_TAG_CLOCK 0x4f01 #define OMAP_TAG_MMC 0x4f02 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 diff --git a/include/hw/dma/xlnx_dpdma.h b/include/hw/dma/xlnx_dpdma.h index 664df28..4090180 100644 --- a/include/hw/dma/xlnx_dpdma.h +++ b/include/hw/dma/xlnx_dpdma.h @@ -53,7 +53,7 @@ typedef struct XlnxDPDMAState XlnxDPDMAState; * data to the buffer specified by * dpdma_set_host_data_location(). * - * Returns The number of bytes transfered by the DPDMA or 0 if an error occured. + * Returns The number of bytes transferred by the DPDMA or 0 if an error occurred. * * @s The DPDMA state. * @channel The channel to start. diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index 94486fd..53b6760 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -180,7 +180,7 @@ typedef struct Q35PCIHost { uint64_t mch_mcfg_base(void); /* - * Arbitary but unique BNF number for IOAPIC device. + * Arbitrary but unique BNF number for IOAPIC device. * * TODO: make sure there would have no conflict with real PCI bus */ diff --git a/include/hw/pci/pcie_aer.h b/include/hw/pci/pcie_aer.h index c2ee4e2..e991d23 100644 --- a/include/hw/pci/pcie_aer.h +++ b/include/hw/pci/pcie_aer.h @@ -40,7 +40,7 @@ struct PCIEAERLog { * The specified value will be clipped down to PCIE_AER_LOG_MAX_LIMIT * to avoid unreasonable memory usage. * I bet that 128 log size would be big enough, otherwise too many errors - * for system to function normaly. But could consecutive errors occur? + * for system to function normally. But could consecutive errors occur? */ #define PCIE_AER_LOG_MAX_DEFAULT 8 #define PCIE_AER_LOG_MAX_LIMIT 128 diff --git a/include/hw/register.h b/include/hw/register.h index 8c12233..e8cfeed 100644 --- a/include/hw/register.h +++ b/include/hw/register.h @@ -92,7 +92,7 @@ struct RegisterInfo { * This structure is used to group all of the individual registers which are * modeled using the RegisterInfo structure. * - * @r is an aray containing of all the relevent RegisterInfo structures. + * @r is an aray containing of all the relevant RegisterInfo structures. * * @num_elements is the number of elements in the array r * diff --git a/include/io/task.h b/include/io/task.h index 42028cb..6810842 100644 --- a/include/io/task.h +++ b/include/io/task.h @@ -231,7 +231,7 @@ void qio_task_complete(QIOTask *task); * * Mark the operation as failed, with @err providing * details about the failure. The @err may be freed - * afer the function returns, as the notification + * after the function returns, as the notification * callback is invoked synchronously. The @task will * be freed when this call completes. */ diff --git a/include/qemu/qht.h b/include/qemu/qht.h index 311139b..56c2c77 100644 --- a/include/qemu/qht.h +++ b/include/qemu/qht.h @@ -72,7 +72,7 @@ void qht_destroy(struct qht *ht); * In case of successful operation, smp_wmb() is implied before the pointer is * inserted into the hash table. * - * Returns true on sucess. + * Returns true on success. * Returns false if the @address@hidden pair already exists in the hash table. */ bool qht_insert(struct qht *ht, void *p, uint32_t hash); diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 3f79a8e..31ba943 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -367,7 +367,7 @@ struct CPUState { /* * Used for events with 'vcpu' and *without* the 'disabled' properties. - * Dynamically allocated based on bitmap requried to hold up to + * Dynamically allocated based on bitmap required to hold up to * trace_get_vcpu_event_count() entries. */ unsigned long *trace_dstate; @@ -758,7 +758,7 @@ extern CPUInterruptHandler cpu_interrupt_handler; /** * cpu_interrupt: * @cpu: The CPU to set an interrupt on. - * @mask: The interupts to set. + * @mask: The interrupts to set. * * Invokes the interrupt handler. */ diff --git a/include/sysemu/char.h b/include/sysemu/char.h index 0a14942..353d756 100644 --- a/include/sysemu/char.h +++ b/include/sysemu/char.h @@ -180,7 +180,7 @@ void qemu_chr_cleanup(void); /** * @qemu_chr_fe_wait_connected: * - * Wait for characted backend to be connected, return < 0 on error or + * Wait for character backend to be connected, return < 0 on error or * if no assicated CharDriver. */ int qemu_chr_fe_wait_connected(CharBackend *be, Error **errp); @@ -436,7 +436,7 @@ void qemu_chr_fe_deinit(CharBackend *b); * @fd_event: event callback * @opaque: an opaque pointer for the callbacks * @context: a main loop context or NULL for the default - * @set_open: whether to call qemu_chr_fe_set_open() implicitely when + * @set_open: whether to call qemu_chr_fe_set_open() implicitly when * any of the handler is non-NULL * * Set the front end char handlers. The front end takes the focus if diff --git a/include/sysemu/cryptodev.h b/include/sysemu/cryptodev.h index 84526c0..f406e8a 100644 --- a/include/sysemu/cryptodev.h +++ b/include/sysemu/cryptodev.h @@ -237,7 +237,7 @@ void cryptodev_backend_free_client( * @backend: the cryptodev backend object * @errp: pointer to a NULL-initialized error object * - * Clean the resouce associated with @backend that realizaed + * Clean the resource associated with @backend that realizaed * by the specific backend's init() callback */ void cryptodev_backend_cleanup( diff --git a/ioport.c b/ioport.c index 94e08ab..3a8de98 100644 --- a/ioport.c +++ b/ioport.c @@ -22,7 +22,7 @@ * THE SOFTWARE. */ /* - * splitted out ioport related stuffs from vl.c. + * split out ioport related stuffs from vl.c. */ #include "qemu/osdep.h" diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 7b77503..c5c4c58 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -7566,7 +7566,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, switch(num) { case TARGET_NR_exit: /* In old applications this may be used to implement _exit(2). - However in threaded applictions it is used for thread termination, + However in threaded applications it is used for thread termination, and _exit_group is used for application termination. Do thread termination if we have more then one thread. */ diff --git a/net/checksum.c b/net/checksum.c index 23323b0..9fe8e6e 100644 --- a/net/checksum.c +++ b/net/checksum.c @@ -69,7 +69,7 @@ void net_checksum_calculate(uint8_t *data, int length) return; } - /* Handle the optionnal VLAN headers */ + /* Handle the optional VLAN headers */ switch (lduw_be_p(&PKT_GET_ETH_HDR(data)->h_proto)) { case ETH_P_VLAN: mac_hdr_len = sizeof(struct eth_header) + @@ -91,7 +91,7 @@ void net_checksum_calculate(uint8_t *data, int length) length -= mac_hdr_len; - /* Now check we have an IP header (with an optionnal VLAN header) */ + /* Now check we have an IP header (with an optional VLAN header) */ if (length < sizeof(struct ip_header)) { return; } diff --git a/net/filter.c b/net/filter.c index 1dfd2ca..2fed6ec 100644 --- a/net/filter.c +++ b/net/filter.c @@ -90,7 +90,7 @@ ssize_t qemu_netfilter_pass_to_next(NetClientState *sender, while (next) { /* * if qemu_netfilter_pass_to_next been called, means that - * the packet has been hold by filter and has already retured size + * the packet has been hold by filter and has already returned size * to the sender, so sent_cb shouldn't be called later, just * pass NULL to next. */ diff --git a/qapi-schema.json b/qapi-schema.json index a0d3b5d..a7966d2 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -3281,7 +3281,7 @@ # # @static: Expand to a static CPU model, a combination of a static base # model name and property delta changes. As the static base model will -# never change, the expanded CPU model will be the same, independant of +# never change, the expanded CPU model will be the same, independent of # independent of QEMU version, machine type, machine options, and # accelerator options. Therefore, the resulting model can be used by # tooling without having to specify a compatibility machine - e.g. when diff --git a/scripts/clean-header-guards.pl b/scripts/clean-header-guards.pl index 54ab99a..3ae79e7 100755 --- a/scripts/clean-header-guards.pl +++ b/scripts/clean-header-guards.pl @@ -19,7 +19,7 @@ # Does the following: # - Header files without a recognizable header guard are skipped. # - Clean up any untidy header guards in-place. Warn if the cleanup -# renames guard symbols, and explain how to find occurences of these +# renames guard symbols, and explain how to find occurrences of these # symbols that may have to be updated manually. # - Warn about duplicate header guard symbols. To make full use of # this warning, you should clean up *all* headers in one run. diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ca5c849..3d92611 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1220,7 +1220,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return aa64; } -/* Function for determing whether guest cp register reads and writes should +/* Function for determining whether guest cp register reads and writes should * access the secure or non-secure bank of a cp register. When EL3 is * operating in AArch32 state, the NS-bit determines whether the secure * instance of a cp register should be used. When EL3 is AArch64 (or if @@ -1879,7 +1879,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, } } - /* The PSTATE bits only mask the interrupt if we have not overriden the + /* The PSTATE bits only mask the interrupt if we have not overridden the * ability above. */ return unmasked || pstate_unmasked; diff --git a/target/arm/helper.c b/target/arm/helper.c index b5b65ca..798203f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2422,7 +2422,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, if (!arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when - * using Long-desciptor translation table format */ + * using Long-descriptor translation table format */ value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); } else if (arm_feature(env, ARM_FEATURE_EL3)) { /* In an implementation that includes the Security Extensions diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6dc27a6..3ed2682 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -382,7 +382,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) { /* We don't need to save all of the syndrome so we mask and shift - * out uneeded bits to help the sleb128 encoder do a better job. + * out unneeded bits to help the sleb128 encoder do a better job. */ syn &= ARM_INSN_START_WORD2_MASK; syn >>= ARM_INSN_START_WORD2_SHIFT; diff --git a/target/cris/helper.c b/target/cris/helper.c index af78cca..47a6c34 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -140,7 +140,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); switch (cs->exception_index) { case EXCP_BREAK: - /* These exceptions are genereated by the core itself. + /* These exceptions are generated by the core itself. ERP should point to the insn following the brk. */ ex_vec = env->trap_vector; env->pregs[PRV10_BRP] = env->pc; @@ -196,7 +196,7 @@ void cris_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_BREAK: - /* These exceptions are genereated by the core itself. + /* These exceptions are generated by the core itself. ERP should point to the insn following the brk. */ ex_vec = env->trap_vector; env->pregs[PR_ERP] = env->pc; @@ -255,7 +255,7 @@ void cris_cpu_do_interrupt(CPUState *cs) undefined. */ env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4); - /* Clear the excption_index to avoid spurios hw_aborts for recursive + /* Clear the excption_index to avoid spurious hw_aborts for recursive bus faults. */ cs->exception_index = -1; diff --git a/target/cris/translate.c b/target/cris/translate.c index b910427..afe41935 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3060,12 +3060,12 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) * On QEMU care needs to be taken when a branch+delayslot sequence is broken * and the branch and delayslot don't share pages. * - * The TB contaning the branch insn will set up env->btarget and evaluate + * The TB containing the branch insn will set up env->btarget and evaluate * env->btaken. When the translation loop exits we will note that the branch * sequence is broken and let env->dslot be the size of the branch insn (those * vary in length). * - * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb + * The TB containing the delayslot will have the PC of its real insn (i.e no lsb * set). It will also expect to have env->dslot setup with the size of the * delay slot so that env->pc - env->dslot point to the branch insn. This TB * will execute the dslot and take the branch, either to btarget or just one diff --git a/target/ppc/STATUS b/target/ppc/STATUS index a4d48a7..1868c17 100644 --- a/target/ppc/STATUS +++ b/target/ppc/STATUS @@ -495,7 +495,7 @@ EXCP KO =============================================================================== PowerPC microcontrollers emulation status -Implemementation should be sufficient to boot Linux: +Implementation should be sufficient to boot Linux: (there seem to be problems with uboot freezing at some point) - PowerPC 405CR - PowerPC 405EP diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2a50c43..819ac9b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2241,7 +2241,7 @@ enum { PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */ PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */ PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ - PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */ + PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */ PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */ }; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 93369d4..409ce29 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -91,7 +91,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } /* new interrupt handler msr preserves existing HV and ME unless - * explicitly overriden + * explicitly overridden */ new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); @@ -139,7 +139,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } } - /* Exception targetting modifiers + /* Exception targeting modifiers * * LPES0 is supported on POWER7/8 * LPES1 is not supported (old iSeries mode) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index fdb7a78..e886803 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -691,7 +691,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, /* Note on LPCR usage: 970 uses HID4, but our special variant * of store_spr copies relevant fields into env->spr[SPR_LPCR]. - * Similarily we filter unimplemented bits when storing into + * Similarly we filter unimplemented bits when storing into * LPCR depending on the MMU version. This code can thus just * use the LPCR "as-is". */ @@ -722,7 +722,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, /* RMA. Check bounds in RMLS */ raddr |= env->spr[SPR_RMOR]; } else { - /* The access failed, generate the approriate interrupt */ + /* The access failed, generate the appropriate interrupt */ if (rwx == 2) { ppc_hash64_set_isi(cs, env, 0x08000000); } else { diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index d09fc0a..1cdf8e5 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -172,7 +172,7 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, } /* Compute access rights */ access = pp_check(ctx->key, pp, ctx->nx); - /* Keep the matching PTE informations */ + /* Keep the matching PTE information */ ctx->raddr = pte1; ctx->prot = access; ret = check_prot(ctx->prot, rw, type); diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h index 136a602..82f098a 100644 --- a/target/s390x/cpu_models.h +++ b/target/s390x/cpu_models.h @@ -23,13 +23,13 @@ typedef struct S390CPUDef { uint8_t gen; /* hw generation identification */ uint16_t type; /* cpu type identification */ uint8_t ec_ga; /* EC GA version (on which also the BC is based) */ - uint8_t mha_pow; /* Maximum Host Adress Power, mha = 2^pow-1 */ + uint8_t mha_pow; /* Maximum Host Address Power, mha = 2^pow-1 */ uint32_t hmfai; /* hypervisor-managed facilities */ /* base/min features, must never be changed between QEMU versions */ S390FeatBitmap base_feat; /* used to init base_feat from generated data */ S390FeatInit base_init; - /* deafault features, QEMU version specific */ + /* default features, QEMU version specific */ S390FeatBitmap default_feat; /* used to init default_feat from generated data */ S390FeatInit default_init; diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 075ff59..d862fc6 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -474,7 +474,7 @@ /* LOAD LOGICAL HALFWORD RELATIVE LONG */ C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0) C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0) -/* LOAD LOGICAL IMMEDATE */ +/* LOAD LOGICAL IMMEDIATE */ D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32) D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0) D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 02bc705..e824e4d 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -344,7 +344,7 @@ static void gen_program_exception(DisasContext *s, int code) { TCGv_i32 tmp; - /* Remember what pgm exeption this was. */ + /* Remember what pgm exception this was. */ tmp = tcg_const_i32(code); tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code)); tcg_temp_free_i32(tmp); @@ -398,7 +398,7 @@ static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2) bool need_31 = !(s->tb->flags & FLAG_MASK_64); /* Note that d2 is limited to 20 bits, signed. If we crop negative - displacements early we create larger immedate addends. */ + displacements early we create larger immediate addends. */ /* Note that addi optimizes the imm==0 case. */ if (b2 && x2) { @@ -776,7 +776,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_SUBU_32: case CC_OP_SUBU_64: - /* Note that CC=0 is impossible; treat it as dont-care. */ + /* Note that CC=0 is impossible; treat it as don't-care. */ switch (mask & 7) { case 2: /* zero -> op1 == op2 */ cond = TCG_COND_EQ; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 478ab55..d196669 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -164,7 +164,7 @@ typedef struct CPUSH4State { uint32_t pteh; /* page table entry high register */ uint32_t ptel; /* page table entry low register */ uint32_t ptea; /* page table entry assistance register */ - uint32_t ttb; /* tranlation table base register */ + uint32_t ttb; /* translation table base register */ uint32_t tea; /* TLB exception address register */ uint32_t tra; /* TRAPA exception register */ uint32_t expevt; /* exception event register */ diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 3118905..8ea2165 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -42,7 +42,7 @@ static int get_physical_address(CPUTriCoreState *env, hwaddr *physical, } #endif -/* TODO: Add exeption support*/ +/* TODO: Add exception support*/ static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, int rw, int tlb_error) { diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 1939d35..edcf1d3 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -57,7 +57,7 @@ static const int tcg_target_call_oarg_regs[1] = { #ifndef CONFIG_SOFTMMU /* Note that XZR cannot be encoded in the address base register slot, - as that actaully encodes SP. So if we need to zero-extend the guest + as that actually encodes SP. So if we need to zero-extend the guest address, via the address index register slot, we need to load even a zero guest base into a register. */ #define USE_GUEST_BASE (guest_base != 0 || TARGET_LONG_BITS == 32) diff --git a/tests/ahci-test.c b/tests/ahci-test.c index ef17629..c5adf77 100644 --- a/tests/ahci-test.c +++ b/tests/ahci-test.c @@ -328,7 +328,7 @@ static void ahci_test_pci_spec(AHCIQState *ahci) ASSERT_BIT_CLEAR(datal, ~0xFF); g_assert_cmphex(datal, !=, 0); - /* Check specification adherence for capability extenstions. */ + /* Check specification adherence for capability extensions. */ data = qpci_config_readw(ahci->dev, datal); switch (ahci->fingerprint) { diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c index 812f830..dc60d7d 100644 --- a/tests/bios-tables-test.c +++ b/tests/bios-tables-test.c @@ -491,7 +491,7 @@ try_again: if (g_file_test(aml_file, G_FILE_TEST_EXISTS)) { exp_sdt.aml_file = aml_file; } else if (*ext != '\0') { - /* try fallback to generic (extention less) expected file */ + /* try fallback to generic (extension less) expected file */ ext = ""; g_free(aml_file); goto try_again; diff --git a/tests/migration/guestperf-batch.py b/tests/migration/guestperf-batch.py index cb150ce..094e819 100755 --- a/tests/migration/guestperf-batch.py +++ b/tests/migration/guestperf-batch.py @@ -1,6 +1,6 @@ #!/usr/bin/python # -# Migration test batch comparison invokation +# Migration test batch comparison invocation # # Copyright (c) 2016 Red Hat, Inc. # diff --git a/tests/migration/guestperf.py b/tests/migration/guestperf.py index 99b027e..0595dd3 100755 --- a/tests/migration/guestperf.py +++ b/tests/migration/guestperf.py @@ -1,6 +1,6 @@ #!/usr/bin/python # -# Migration test direct invokation command +# Migration test direct invocation command # # Copyright (c) 2016 Red Hat, Inc. # diff --git a/tests/postcopy-test.c b/tests/postcopy-test.c index dafe8be..05eea8c 100644 --- a/tests/postcopy-test.c +++ b/tests/postcopy-test.c @@ -77,7 +77,7 @@ static bool ufd_version_check(void) static const char *tmpfs; /* A simple PC boot sector that modifies memory (1-100MB) quickly - * outputing a 'B' every so often if it's still running. + * outputting a 'B' every so often if it's still running. */ unsigned char bootsect[] = { 0xfa, 0x0f, 0x01, 0x16, 0x74, 0x7c, 0x66, 0xb8, 0x01, 0x00, 0x00, 0x00, diff --git a/tests/test-throttle.c b/tests/test-throttle.c index 363b59a..c8aa0e8 100644 --- a/tests/test-throttle.c +++ b/tests/test-throttle.c @@ -132,7 +132,7 @@ static void test_compute_wait(void) g_assert(double_cmp(bkt.burst_level, 0)); g_assert(double_cmp(bkt.level, (i + 1) * (bkt.max - bkt.avg) / 10)); /* We can do bursts for the 2 seconds we have configured in - * burst_length. We have 100 extra miliseconds of burst + * burst_length. We have 100 extra milliseconds of burst * because bkt.level has been leaking during this time. * After that, we have to wait. */ result = i < 21 ? 0 : 1.8 * NANOSECONDS_PER_SECOND; diff --git a/trace-events b/trace-events index f74e1d3..88edff5 100644 --- a/trace-events +++ b/trace-events @@ -154,7 +154,7 @@ vcpu guest_cpu_reset(void) # uint8_t size_shift : 2; /* interpreted as "1 << size_shift" bytes */ # bool sign_extend: 1; /* sign-extended */ # uint8_t endianness : 1; /* 0: little, 1: big */ -# bool store : 1; /* wheter it's a store operation */ +# bool store : 1; /* whether it's a store operation */ # }; # # Mode: user, softmmu diff --git a/util/qemu-progress.c b/util/qemu-progress.c index f745233..cacbb9a 100644 --- a/util/qemu-progress.c +++ b/util/qemu-progress.c @@ -92,7 +92,7 @@ static void progress_dummy_init(void) /* * SIGUSR1 is SIG_IPI and gets blocked in qemu_init_main_loop(). In the * tools that use the progress report SIGUSR1 isn't used in this meaning - * and instead should print the progress, so reenable it. + * and instead should print the progress, so re-enable it. */ sigemptyset(&set); sigaddset(&set, SIGUSR1); @@ -128,7 +128,7 @@ void qemu_progress_end(void) /* * Report progress. * @delta is how much progress we made. - * If @max is zero, @delta is an absolut value of the total job done. + * If @max is zero, @delta is an absolute value of the total job done. * Else, @delta is a progress delta since the last call, as a fraction * of @max. I.e. the delta is @delta * @max / 100. This allows * relative accounting of functions which may be a different fraction of diff --git a/util/qemu-sockets.c b/util/qemu-sockets.c index fe1d07a..5b283c1 100644 --- a/util/qemu-sockets.c +++ b/util/qemu-sockets.c @@ -388,7 +388,7 @@ static struct addrinfo *inet_parse_connect_saddr(InetSocketAddress *saddr, /* At least FreeBSD and OS-X 10.6 declare AI_V4MAPPED but * then don't implement it in their getaddrinfo(). Detect - * this and retry without the flag since that's preferrable + * this and retry without the flag since that's preferable * to a fatal error */ if (rc == EAI_BADFLAGS && diff --git a/util/qemu-thread-win32.c b/util/qemu-thread-win32.c index 728e76b..c89f7c5 100644 --- a/util/qemu-thread-win32.c +++ b/util/qemu-thread-win32.c @@ -340,7 +340,7 @@ void qemu_event_wait(QemuEvent *ev) ResetEvent(ev->event); /* Tell qemu_event_set that there are waiters. No need to retry - * because there cannot be a concurent busy->free transition. + * because there cannot be a concurrent busy->free transition. * After the CAS, the event will be either set or busy. */ if (atomic_cmpxchg(&ev->value, EV_FREE, EV_BUSY) == EV_SET) { diff --git a/util/qht.c b/util/qht.c index ff4d2e6..c45435b 100644 --- a/util/qht.c +++ b/util/qht.c @@ -49,7 +49,7 @@ * it anymore. * * Writers check for concurrent resizes by comparing ht->map before and after - * acquiring their bucket lock. If they don't match, a resize has occured + * acquiring their bucket lock. If they don't match, a resize has occurred * while the bucket spinlock was being acquired. * * Related Work: diff --git a/util/uri.c b/util/uri.c index 70a9cbc..4484637 100644 --- a/util/uri.c +++ b/util/uri.c @@ -342,7 +342,7 @@ rfc3986_parse_port(URI *uri, const char **str) * @uri: pointer to an URI structure * @str: the string to analyze * - * Parse an user informations part and fills in the appropriate fields + * Parse an user information part and fills in the appropriate fields * of the @uri structure * * userinfo = *( unreserved / pct-encoded / sub-delims / ":" ) -- 2.1.4