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[Qemu-devel] [PULL 18/25] aspeed: add the definitions for the AST2400 A1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 18/25] aspeed: add the definitions for the AST2400 A1 SoC |
Date: |
Tue, 27 Dec 2016 15:21:10 +0000 |
From: Cédric Le Goater <address@hidden>
There is not much differences with the A0 revision apart from the DDR
calibration.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/misc/aspeed_scu.h | 1 +
hw/arm/aspeed_soc.c | 10 ++++++++++
hw/misc/aspeed_scu.c | 2 ++
hw/misc/aspeed_sdmc.c | 3 +++
4 files changed, 16 insertions(+)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 14ffc43..bd4ac01 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -32,6 +32,7 @@ typedef struct AspeedSCUState {
} AspeedSCUState;
#define AST2400_A0_SILICON_REV 0x02000303U
+#define AST2400_A1_SILICON_REV 0x02010303U
#define AST2500_A0_SILICON_REV 0x04000303U
#define AST2500_A1_SILICON_REV 0x04010303U
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 233a6b9..d111d2e 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -59,6 +59,16 @@ static const AspeedSoCInfo aspeed_socs[] = {
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
}, {
+ .name = "ast2400-a1",
+ .cpu_model = "arm926",
+ .silicon_rev = AST2400_A1_SILICON_REV,
+ .sdram_base = AST2400_SDRAM_BASE,
+ .sram_size = 0x8000,
+ .spis_num = 1,
+ .spi_bases = aspeed_soc_ast2400_spi_bases,
+ .fmc_typename = "aspeed.smc.fmc",
+ .spi_typename = aspeed_soc_ast2400_typenames,
+ }, {
.name = "ast2400",
.cpu_model = "arm926",
.silicon_rev = AST2400_A0_SILICON_REV,
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index b1f3e6f..34e8638 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -231,6 +231,7 @@ static void aspeed_scu_reset(DeviceState *dev)
switch (s->silicon_rev) {
case AST2400_A0_SILICON_REV:
+ case AST2400_A1_SILICON_REV:
reset = ast2400_a0_resets;
break;
case AST2500_A0_SILICON_REV:
@@ -249,6 +250,7 @@ static void aspeed_scu_reset(DeviceState *dev)
static uint32_t aspeed_silicon_revs[] = {
AST2400_A0_SILICON_REV,
+ AST2400_A1_SILICON_REV,
AST2500_A0_SILICON_REV,
AST2500_A1_SILICON_REV,
};
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 8830dc0..5f3ac0b 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -119,6 +119,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr,
uint64_t data,
/* Make sure readonly bits are kept */
switch (s->silicon_rev) {
case AST2400_A0_SILICON_REV:
+ case AST2400_A1_SILICON_REV:
data &= ~ASPEED_SDMC_READONLY_MASK;
break;
case AST2500_A0_SILICON_REV:
@@ -193,6 +194,7 @@ static void aspeed_sdmc_reset(DeviceState *dev)
/* Set ram size bit and defaults values */
switch (s->silicon_rev) {
case AST2400_A0_SILICON_REV:
+ case AST2400_A1_SILICON_REV:
s->regs[R_CONF] |=
ASPEED_SDMC_VGA_COMPAT |
ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
@@ -224,6 +226,7 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error
**errp)
switch (s->silicon_rev) {
case AST2400_A0_SILICON_REV:
+ case AST2400_A1_SILICON_REV:
s->ram_bits = ast2400_rambits(s);
break;
case AST2500_A0_SILICON_REV:
--
2.7.4
- [Qemu-devel] [PULL 08/25] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset, (continued)
- [Qemu-devel] [PULL 08/25] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 09/25] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 10/25] hw/arm/virt: add 2.9 machine type, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 11/25] m25p80: add support for the mx66l1g45g, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 12/25] aspeed: QOMify the CPU object and attach it to the SoC, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 13/25] aspeed: remove cannot_destroy_with_object_finalize_yet, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 14/25] aspeed: attach the second SPI controller object to the SoC, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 15/25] aspeed: extend the board configuration with flash models, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 16/25] aspeed: add support for the romulus-bmc board, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 17/25] aspeed: add a memory region for SRAM, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 18/25] aspeed: add the definitions for the AST2400 A1 SoC,
Peter Maydell <=
- [Qemu-devel] [PULL 19/25] aspeed: change SoC revision of the palmetto-bmc machine, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 20/25] aspeed/scu: fix SCU region size, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 21/25] aspeed/smc: improve segment register support, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 22/25] aspeed/smc: set the number of flash modules for the FMC controller, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 23/25] hw/arm: remove trailing whitespace, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 24/25] hw/i2c: Add a NULL check for i2c slave init callbacks, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 25/25] target-arm: Add VBAR support to ARM1176 CPUs, Peter Maydell, 2016/12/27
- Re: [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2016/12/27