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Re: [Qemu-devel] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruct
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruction |
Date: |
Fri, 9 Dec 2016 09:51:03 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Wed, Dec 07, 2016 at 11:55:01PM +0530, Nikunj A Dadhania wrote:
> xscpsgnqp: VSX Scalar Copy Sign Quad-Precision
>
> Signed-off-by: Nikunj A Dadhania <address@hidden>
> Reviewed-by: Richard Henderson <address@hidden>
Merged to ppc-for-2.9
> ---
> target-ppc/translate/vsx-impl.inc.c | 12 +++++++++++-
> target-ppc/translate/vsx-ops.inc.c | 1 +
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/target-ppc/translate/vsx-impl.inc.c
> b/target-ppc/translate/vsx-impl.inc.c
> index 01b95df..8321134 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -642,9 +642,10 @@ VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
> #define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
> static void glue(gen_, name)(DisasContext *ctx) \
> { \
> + int xa; \
> int xt = rD(ctx->opcode) + 32; \
> int xb = rB(ctx->opcode) + 32; \
> - TCGv_i64 xbh, xbl, sgm; \
> + TCGv_i64 xah, xbh, xbl, sgm; \
> \
> if (unlikely(!ctx->vsx_enabled)) { \
> gen_exception(ctx, POWERPC_EXCP_VSXU); \
> @@ -666,6 +667,14 @@ static void glue(gen_, name)(DisasContext *ctx)
> \
> case OP_NEG: \
> tcg_gen_xor_i64(xbh, xbh, sgm); \
> break; \
> + case OP_CPSGN: \
> + xah = tcg_temp_new_i64(); \
> + xa = rA(ctx->opcode) + 32; \
> + tcg_gen_and_i64(xah, cpu_vsrh(xa), sgm); \
> + tcg_gen_andc_i64(xbh, xbh, sgm); \
> + tcg_gen_or_i64(xbh, xbh, xah); \
> + tcg_temp_free_i64(xah); \
> + break; \
> } \
> tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
> tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
> @@ -677,6 +686,7 @@ static void glue(gen_, name)(DisasContext *ctx)
> \
> VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
> VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
> VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
> +VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP)
>
> #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
> static void glue(gen_, name)(DisasContext * ctx) \
> diff --git a/target-ppc/translate/vsx-ops.inc.c
> b/target-ppc/translate/vsx-ops.inc.c
> index d798edb..42e83d2 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -107,6 +107,7 @@ GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
> GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
> GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
> GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
> +GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
>
> GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
> GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-devel] [PATCH v1 3/9] target-ppc: implement stxvl instruction, (continued)
- [Qemu-devel] [PATCH v1 3/9] target-ppc: implement stxvl instruction, Nikunj A Dadhania, 2016/12/07
- [Qemu-devel] [PATCH v1 5/9] target-ppc: implement xxextractuw instruction, Nikunj A Dadhania, 2016/12/07
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- [Qemu-devel] [PATCH v1 7/9] target-ppc: implement xsnegqp instruction, Nikunj A Dadhania, 2016/12/07
- [Qemu-devel] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruction, Nikunj A Dadhania, 2016/12/07
- Re: [Qemu-devel] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruction,
David Gibson <=
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