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Re: [Qemu-devel] [PATCH 2/9] target-ppc: Fix xscmpodp and xscmpudp instr
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH 2/9] target-ppc: Fix xscmpodp and xscmpudp instructions |
Date: |
Thu, 24 Nov 2016 12:29:40 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Wed, Nov 23, 2016 at 11:10:08AM +0530, Bharata B Rao wrote:
> On Wed, Nov 23, 2016 at 03:01:18PM +1100, David Gibson wrote:
> > On Tue, Nov 22, 2016 at 05:15:58PM +0530, Nikunj A Dadhania wrote:
> > > From: Bharata B Rao <address@hidden>
> > >
> > > - xscmpodp & xscmpudp are missing flags reset.
> > > - In xscmpodp, VXCC should be set only if VE is 0 for signalling NaN case
> > > and VXCC should be set by explicitly checking for quiet NaN case.
> > > - Comparison is being done only if the operands are not NaNs. However as
> > > per ISA, it should be done even when operands are NaNs.
> >
> > For my interest, can you explain the difference between ordered and
> > unordered comparisons? I looked at the ISA and mostly just became
> > confused.
>
> >From another section of the same ISA doc, I see these description which
> makes the distinction between ordered and unordered comparisions a bit
> more clear.
>
> Unordered:
>
> "If either of the operands is a NaN, either quiet or signal-
> ing, then CR field BF and the FPCC are set to reflect
> unordered. If either of the operands is a Signaling NaN,
> then VXSNAN is set."
>
> Ordered:
>
> "If either of the operands is a NaN, either quiet or signal-
> ing, then CR field BF and the FPCC are set to reflect
> unordered. If either of the operands is a Signaling NaN,
> then VXSNAN is set and, if Invalid Operation is dis-
> abled (VE=0), VXVC is set. If neither operand is a Sig-
> naling NaN but at least one operand is a Quiet NaN,
> then VXVC is set."
Ah, thanks. So it's basically just the setting of VXVC which differs.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-devel] [PATCH ppc-for-2.9 0/9] POWER9 TCG enablements - part8, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 3/9] target-ppc: Add xscmpexp[dp, qp] instructions, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 9/9] target-ppc: add vextu[bhw]rx instructions, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 7/9] target-ppc: implement lxv/lxvx and stxv/stxvx, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 6/9] target-ppc: implement stxsd and stxssp, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 8/9] target-ppc: add vextu[bhw]lx instructions, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 5/9] target-ppc: implement lxsd and lxssp instructions, Nikunj A Dadhania, 2016/11/22