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[Qemu-devel] [PATCH v4 23/64] tcg: Allow an operand to be matching or a
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 23/64] tcg: Allow an operand to be matching or a constant |
Date: |
Wed, 23 Nov 2016 14:01:20 +0100 |
This allows an output operand to match an input operand
only when the input operand needs a register.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg.c | 63 ++++++++++++++++++++++++++++++++-------------------------------
1 file changed, 32 insertions(+), 31 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 8b4dce7..cb898f1 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1256,37 +1256,37 @@ static void process_op_defs(TCGContext *s)
tcg_regset_clear(def->args_ct[i].u.regs);
def->args_ct[i].ct = 0;
- if (ct_str[0] >= '0' && ct_str[0] <= '9') {
- int oarg;
- oarg = ct_str[0] - '0';
- tcg_debug_assert(oarg < def->nb_oargs);
- tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
- /* TCG_CT_ALIAS is for the output arguments. The input
- argument is tagged with TCG_CT_IALIAS. */
- def->args_ct[i] = def->args_ct[oarg];
- def->args_ct[oarg].ct = TCG_CT_ALIAS;
- def->args_ct[oarg].alias_index = i;
- def->args_ct[i].ct |= TCG_CT_IALIAS;
- def->args_ct[i].alias_index = oarg;
- } else {
- for(;;) {
- if (*ct_str == '\0')
- break;
- switch(*ct_str) {
- case '&':
- def->args_ct[i].ct |= TCG_CT_NEWREG;
- ct_str++;
- break;
- case 'i':
- def->args_ct[i].ct |= TCG_CT_CONST;
- ct_str++;
- break;
- default:
- ct_str = target_parse_constraint(&def->args_ct[i],
- ct_str, type);
- /* Typo in TCGTargetOpDef constraint. */
- tcg_debug_assert(ct_str != NULL);
+ while (*ct_str != '\0') {
+ switch(*ct_str) {
+ case '0' ... '9':
+ {
+ int oarg = *ct_str - '0';
+ tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
+ tcg_debug_assert(oarg < def->nb_oargs);
+ tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
+ /* TCG_CT_ALIAS is for the output arguments.
+ The input is tagged with TCG_CT_IALIAS. */
+ def->args_ct[i] = def->args_ct[oarg];
+ def->args_ct[oarg].ct |= TCG_CT_ALIAS;
+ def->args_ct[oarg].alias_index = i;
+ def->args_ct[i].ct |= TCG_CT_IALIAS;
+ def->args_ct[i].alias_index = oarg;
}
+ ct_str++;
+ break;
+ case '&':
+ def->args_ct[i].ct |= TCG_CT_NEWREG;
+ ct_str++;
+ break;
+ case 'i':
+ def->args_ct[i].ct |= TCG_CT_CONST;
+ ct_str++;
+ break;
+ default:
+ ct_str = target_parse_constraint(&def->args_ct[i],
+ ct_str, type);
+ /* Typo in TCGTargetOpDef constraint. */
+ tcg_debug_assert(ct_str != NULL);
}
}
}
@@ -2296,7 +2296,8 @@ static void tcg_reg_alloc_op(TCGContext *s,
arg = args[i];
arg_ct = &def->args_ct[i];
ts = &s->temps[arg];
- if (arg_ct->ct & TCG_CT_ALIAS) {
+ if ((arg_ct->ct & TCG_CT_ALIAS)
+ && !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index];
} else if (arg_ct->ct & TCG_CT_NEWREG) {
reg = tcg_reg_alloc(s, arg_ct->u.regs,
--
2.7.4
- [Qemu-devel] [PATCH v4 14/64] target-arm: Use new deposit and extract ops, (continued)
- [Qemu-devel] [PATCH v4 14/64] target-arm: Use new deposit and extract ops, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 16/64] target-mips: Use the new extract op, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 15/64] target-i386: Use new deposit and extract ops, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 17/64] target-ppc: Use the new deposit and extract ops, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 19/64] tcg/optimize: Fold movcond 0/1 into setcond, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 18/64] target-s390x: Use the new deposit and extract ops, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 20/64] tcg: Add markup for output requires new register, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 22/64] tcg: Pass the opcode width to target_parse_constraint, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 21/64] tcg: Transition flat op_defs array to a target callback, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 25/64] disas/i386.c: Handle tzcnt, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 23/64] tcg: Allow an operand to be matching or a constant,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 26/64] disas/ppc: Handle popcnt and cnttz, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 24/64] tcg: Add clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 27/64] target-alpha: Use the ctz and clz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 29/64] target-microblaze: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 28/64] target-cris: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 31/64] target-openrisc: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 30/64] target-mips: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 32/64] target-ppc: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 33/64] target-s390x: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 34/64] target-tilegx: Use clz and ctz opcodes, Richard Henderson, 2016/11/23