[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v1 23/30] target-sparc: implement auto-demapping for
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v1 23/30] target-sparc: implement auto-demapping for UA2005 CPUs |
Date: |
Fri, 4 Nov 2016 21:50:24 +0100 |
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target-sparc/ldst_helper.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 0447d4e..57b3b97 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -210,6 +210,28 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
{
unsigned int i, replace_used;
+ if (cpu_has_hypervisor(env1)) {
+ uint64_t new_vaddr = tlb_tag & ~0x1fffULL;
+ uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte);
+ uint32_t new_ctx = tlb_tag & 0x1fffU;
+ for (i = 0; i < 64; i++) {
+ uint32_t ctx = tlb[i].tag & 0x1fffU;
+ /* check if new mapping overlaps an existing one */
+ if (new_ctx == ctx) {
+ uint64_t vaddr = tlb[i].tag & ~0x1fffULL;
+ uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte);
+ if (new_vaddr == vaddr
+ || (new_vaddr < vaddr + size
+ && vaddr < new_vaddr + new_size)) {
+ DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr,
+ new_vaddr);
+ replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
+ return;
+ }
+ }
+
+ }
+ }
/* Try replacing invalid entry */
for (i = 0; i < 64; i++) {
if (!TTE_IS_VALID(tlb[i].tte)) {
--
1.8.3.1
- [Qemu-devel] [PATCH v1 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, (continued)
- [Qemu-devel] [PATCH v1 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 18/30] target-sparc: replace the last tlb entry when no free entries left, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 15/30] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 20/30] target-sparc: implement UA2005 TSB Pointers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 21/30] target-sparc: simplify ultrasparc_tsb_pointer, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 23/30] target-sparc: implement auto-demapping for UA2005 CPUs,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v1 22/30] target-sparc: allow 256M sized pages, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 24/30] target-sparc: add more registers to dump_mmu, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 25/30] target-sparc: implement UA2005 ASI_MMU (0x21), Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 28/30] target-sparc: implement sun4v RTC, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 29/30] target-sparc: move common cpu initialisation routines to sparc64.c, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 30/30] target-sparc: fix up niagara machine, Artyom Tarasenko, 2016/11/04