[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix.
From: |
Julian Brown |
Subject: |
[Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix. |
Date: |
Thu, 3 Nov 2016 10:30:57 -0700 |
In BE32 mode, sub-word size watchpoints can fail to trigger because the
address of the access is adjusted in the opcode helpers before being
compared with the watchpoint registers. This patch reversed the address
adjustment before performing the comparison.
Signed-off-by: Julian Brown <address@hidden>
---
exec.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/exec.c b/exec.c
index 4c84389..eadab54 100644
--- a/exec.c
+++ b/exec.c
@@ -2047,6 +2047,19 @@ static void check_watchpoint(int offset, int len,
MemTxAttrs attrs, int flags)
return;
}
vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
+#if defined(TARGET_ARM) && !defined(CONFIG_USER_ONLY)
+ /* In BE32 system mode, target memory is stored byteswapped (FIXME:
+ relative to a little-endian host system), and by the time we reach here
+ (via an opcode helper) the addresses of subword accesses have been
+ adjusted to account for that, which means that watchpoints will not
+ match. Undo the adjustment here. */
+ if (arm_sctlr_b(env)) {
+ if (len == 1)
+ vaddr ^= 3;
+ else if (len == 2)
+ vaddr ^= 2;
+ }
+#endif
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (cpu_watchpoint_address_matches(wp, vaddr, len)
&& (wp->flags & flags)) {
--
1.9.1
[Qemu-devel] [PATCH 3/5] Fix arm_semi_flen_cb for BE32 system mode., Julian Brown, 2016/11/03
[Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix.,
Julian Brown <=
[Qemu-devel] [PATCH 5/5] Fix typo in arm_cpu_do_interrupt_aarch32., Julian Brown, 2016/11/03
Re: [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub), no-reply, 2016/11/03
Re: [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub), no-reply, 2016/11/03