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[Qemu-devel] [PULL 03/18] target-m68k: add exg ops
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PULL 03/18] target-m68k: add exg ops |
Date: |
Fri, 28 Oct 2016 10:48:17 +0200 |
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-m68k/translate.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 0d3111d..b407623 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2021,6 +2021,33 @@ DISAS_INSN(eor)
DEST_EA(env, insn, OS_LONG, dest, &addr);
}
+static void do_exg(TCGv reg1, TCGv reg2)
+{
+ TCGv temp = tcg_temp_new();
+ tcg_gen_mov_i32(temp, reg1);
+ tcg_gen_mov_i32(reg1, reg2);
+ tcg_gen_mov_i32(reg2, temp);
+ tcg_temp_free(temp);
+}
+
+DISAS_INSN(exg_aa)
+{
+ /* exchange Dx and Dy */
+ do_exg(DREG(insn, 9), DREG(insn, 0));
+}
+
+DISAS_INSN(exg_dd)
+{
+ /* exchange Ax and Ay */
+ do_exg(AREG(insn, 9), AREG(insn, 0));
+}
+
+DISAS_INSN(exg_da)
+{
+ /* exchange Dx and Ay */
+ do_exg(DREG(insn, 9), AREG(insn, 0));
+}
+
DISAS_INSN(and)
{
TCGv src;
@@ -3154,6 +3181,9 @@ void register_m68k_insns (CPUM68KState *env)
INSN(cmpa, b0c0, f0c0, M68000);
INSN(eor, b180, f1c0, CF_ISA_A);
BASE(and, c000, f000);
+ INSN(exg_dd, c140, f1f8, M68000);
+ INSN(exg_aa, c148, f1f8, M68000);
+ INSN(exg_da, c188, f1f8, M68000);
BASE(mulw, c0c0, f0c0);
BASE(addsub, d000, f000);
INSN(addx, d180, f1f8, CF_ISA_A);
--
2.7.4
- [Qemu-devel] [PULL 00/18] M68k part2 patches, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 10/18] target-m68k: and can manage word and byte operands, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 05/18] target-m68k: add dbcc, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 02/18] target-m68k: add linkl, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 11/18] target-m68k: suba/adda can manage word operand, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 03/18] target-m68k: add exg ops,
Laurent Vivier <=
- [Qemu-devel] [PULL 17/18] target-m68k: immediate ops manage word and byte operands, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 01/18] target-m68k: add bkpt instruction, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 07/18] target-m68k: add addressing modes to not, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 14/18] target-m68k: add addressing modes to neg, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 16/18] target-m68k: cmp manages word and bytes operands, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 13/18] target-m68k: introduce byte and word cc_ops, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 18/18] MAINTAINERS: update M68K entry, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 09/18] target-m68k: or can manage word and byte operands, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 06/18] target-m68k: Inline addx, subx, negx, Laurent Vivier, 2016/10/28
- [Qemu-devel] [PULL 04/18] target-m68k: add addressing modes to scc, Laurent Vivier, 2016/10/28