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[Qemu-devel] [PATCH v5 24/33] cputlb: add assert_cpu_is_self checks
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v5 24/33] cputlb: add assert_cpu_is_self checks |
Date: |
Thu, 27 Oct 2016 16:10:21 +0100 |
For SoftMMU the TLB flushes are an example of a task that can be
triggered on one vCPU by another. To deal with this properly we need to
use safe work to ensure these changes are done safely. The new assert
can be enabled while debugging to catch these cases.
Signed-off-by: Alex Bennée <address@hidden>
---
cputlb.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/cputlb.c b/cputlb.c
index 986efaa..eec1c39 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -59,6 +59,12 @@
} \
} while (0)
+#define assert_cpu_is_self(this_cpu) do { \
+ if (DEBUG_TLB_GATE) { \
+ g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \
+ } \
+ } while (0)
+
/* statistics */
int tlb_flush_count;
@@ -78,6 +84,7 @@ void tlb_flush(CPUState *cpu, int flush_global)
{
CPUArchState *env = cpu->env_ptr;
+ assert_cpu_is_self(cpu);
tlb_debug("(%d)\n", flush_global);
memset(env->tlb_table, -1, sizeof(env->tlb_table));
@@ -94,6 +101,7 @@ static inline void v_tlb_flush_by_mmuidx(CPUState *cpu,
va_list argp)
{
CPUArchState *env = cpu->env_ptr;
+ assert_cpu_is_self(cpu);
tlb_debug("start\n");
for (;;) {
@@ -138,6 +146,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
int i;
int mmu_idx;
+ assert_cpu_is_self(cpu);
tlb_debug("page :" TARGET_FMT_lx "\n", addr);
/* Check if we need to flush due to large pages. */
@@ -175,6 +184,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong
addr, ...)
va_start(argp, addr);
+ assert_cpu_is_self(cpu);
tlb_debug("addr "TARGET_FMT_lx"\n", addr);
/* Check if we need to flush due to large pages. */
@@ -263,6 +273,8 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1,
ram_addr_t length)
int mmu_idx;
+ assert_cpu_is_self(cpu);
+
env = cpu->env_ptr;
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
unsigned int i;
@@ -294,6 +306,8 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
int i;
int mmu_idx;
+ assert_cpu_is_self(cpu);
+
vaddr &= TARGET_PAGE_MASK;
i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
@@ -353,6 +367,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong
vaddr,
unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;
int asidx = cpu_asidx_from_attrs(cpu, attrs);
+ assert_cpu_is_self(cpu);
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
tlb_add_large_page(env, vaddr, size);
--
2.10.1
- Re: [Qemu-devel] [PATCH v5 14/33] tcg: add kick timer for single-threaded vCPU emulation, (continued)
- [Qemu-devel] [PATCH v5 13/33] tcg: add options for enabling MTTCG, Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 17/33] cpus: re-factor out handle_icount_deadline, Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 22/33] atomic: introduce cmpxchg_bool, Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 16/33] tcg: drop global lock during TCG code execution, Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 18/33] tcg: remove global exit_request, Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 15/33] tcg: rename tcg_current_cpu to tcg_current_rr_cpu, Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 06/33] tcg: comment on which functions have to be called with tb_lock held, Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 11/33] tcg: move tcg_exec_all and helpers above thread fn, Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 27/33] cputlb: atomically update tlb fields used by tlb_reset_dirty, Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 24/33] cputlb: add assert_cpu_is_self checks,
Alex Bennée <=
- [Qemu-devel] [PATCH v5 25/33] cputlb: introduce tlb_flush_* async work., Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 31/33] target-arm: ensure BQL taken for ARM_CP_IO register access, Alex Bennée, 2016/10/27
- [Qemu-devel] [PATCH v5 30/33] target-arm/cpu: don't reset TLB structures, use cputlb to do it, Alex Bennée, 2016/10/27
[Qemu-devel] [PATCH v5 19/33] tcg: move locking for tb_invalidate_phys_page_range up, Alex Bennée, 2016/10/27
[Qemu-devel] [PATCH v5 21/33] tcg: enable thread-per-vCPU, Alex Bennée, 2016/10/27
[Qemu-devel] [PATCH v5 33/33] tcg: enable MTTCG by default for ARM on x86 hosts, Alex Bennée, 2016/10/27