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From: | Richard Henderson |
Subject: | Re: [Qemu-devel] [PATCH 03/16] target-m68k: add exg ops |
Date: | Wed, 26 Oct 2016 15:07:08 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 |
On 10/26/2016 09:35 AM, Laurent Vivier wrote:
+ INSN(undef, c140, f1f8, CF_ISA_A); + INSN(exg, c140, f1f8, M68000); + INSN(undef, c148, f1f8, CF_ISA_A); + INSN(exg, c148, f1f8, M68000); + INSN(undef, c188, f1f8, CF_ISA_A); + INSN(exg, c188, f1f8, M68000);
Given that we started with + BASE(undef, 0000, 0000); why do we need to re-add these undef's? Otherwise, why not use these, and a helper, to avoid having to re-decode. static void do_exg(TCGv reg1, TCGv reg2) { TCGv temp = tcg_temp_new(); tcg_gen_mov_i32(temp, reg1); tcg_gen_mov_i32(reg1, reg2); tcg_gen_mov_i32(reg2, temp); tcg_temp_free(temp); } DISAS_INSN(exg_dd) { do_exg(DREG(insn, 9), DREG(insn, 0)); } DISAS_INSN(exg_aa) { do_exg(AREG(insn, 9), AREG(insn, 0)); } DISAS_INSN(exg_da) { do_exg(DREG(insn, 9), AREG(insn, 0)); } r~
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