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[Qemu-devel] [PULL 21/23] target-m68k: Use setcond for scc
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PULL 21/23] target-m68k: Use setcond for scc |
Date: |
Tue, 25 Oct 2016 21:03:17 +0200 |
From: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 4a650e1..5cc5e14 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -865,19 +865,21 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel
*l1)
DISAS_INSN(scc)
{
- TCGLabel *l1;
+ DisasCompare c;
int cond;
- TCGv reg;
+ TCGv reg, tmp;
- l1 = gen_new_label();
cond = (insn >> 8) & 0xf;
+ gen_cc_cond(&c, s, cond);
+
+ tmp = tcg_temp_new();
+ tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
+ free_cond(&c);
+
reg = DREG(insn, 0);
- tcg_gen_andi_i32(reg, reg, 0xffffff00);
- /* This is safe because we modify the reg directly, with no other values
- live. */
- gen_jmpcc(s, cond ^ 1, l1);
- tcg_gen_ori_i32(reg, reg, 0xff);
- gen_set_label(l1);
+ tcg_gen_neg_i32(tmp, tmp);
+ tcg_gen_deposit_i32(reg, reg, tmp, 0, 8);
+ tcg_temp_free(tmp);
}
/* Force a TB lookup after an instruction that changes the CPU state. */
--
2.7.4
- [Qemu-devel] [PULL 00/23] M68k part1 patches, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 06/23] target-m68k: set disassembler mode to 680x0 or coldfire, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 09/23] target-m68k: REG() macro cleanup, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 04/23] target-m68k: manage scaled index, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 01/23] target-m68k: fix DEBUG_DISPATCH, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 02/23] target-m68k: Build the opcode table only once to avoid multithreading issues, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 03/23] target-m68k: define m680x0 CPUs and features, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 15/23] target-m68k: update CPU flags management, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 13/23] target-m68k: update move to/from ccr/sr, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 21/23] target-m68k: Use setcond for scc,
Laurent Vivier <=
- [Qemu-devel] [PULL 08/23] target-m68k: set PAGE_BITS to 12 for m68k, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 07/23] target-m68k: define operand sizes, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 12/23] target-m68k: remove m68k_cpu_exec_enter() and m68k_cpu_exec_exit(), Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 05/23] target-m68k: introduce read_imXX() functions, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 11/23] target-m68k: Replace helper_xflag_lt with setcond, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 10/23] target-m68k: allow to update flags with operation on words and bytes, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 23/23] target-m68k: Optimize gen_flush_flags, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 20/23] target-m68k: Introduce DisasCompare, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 16/23] target-m68k: Print flags properly, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PULL 18/23] target-m68k: Remove incorrect clearing of cc_x, Laurent Vivier, 2016/10/25