Re: [Qemu-devel] [PATCH v2 07/18] tcg/i386: Implement field extraction opcodes

[Paolo Bonzini]

On 18/10/2016 17:10, Richard Henderson wrote:
> +    case INDEX_op_extract_i32:
> +        /* On the off-chance that we can use the high-byte registers.
> +           Otherwise we emit the same ext16 + shift pattern that we
> +           would have gotten from the normal tcg-op.c expansion.  */
> +        tcg_debug_assert(args[2] == 8 && args[3] == 8);
> +        if (args[1] < 4 && args[0] < 8) {
> +            tcg_out_modrm(s, OPC_MOVZBL, args[0], args[1] + 4);
> +        } else {
> +            tcg_out_ext16u(s, args[0], args[1]);
> +            tcg_out_shifti(s, SHIFT_SHR, args[0], 8);
> +        }

Since the opcode is pretty rare, perhaps it's worth restricting the
constraints to, respectively, a new constraint for 0xff ("R"?) and "Q"?
It should generate slightly better code without constraining the
register allocator too much.

Paolo