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[Qemu-devel] [PATCH v2 01/15] target-sparc: Use overalignment flags for
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 01/15] target-sparc: Use overalignment flags for twinx and block asis |
Date: |
Tue, 18 Oct 2016 19:34:16 -0700 |
This allows us to enforce 16 and 64-byte alignment
without any extra overhead.
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
---
target-sparc/translate.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index e7691e4..ec4a73a 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2385,20 +2385,23 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
case GET_ASI_BLOCK:
/* Valid for lddfa on aligned registers only. */
if (size == 8 && (rd & 7) == 0) {
+ TCGMemOp memop;
TCGv eight;
int i;
- gen_check_align(addr, 0x3f);
gen_address_mask(dc, addr);
+ /* The first operation checks required alignment. */
+ memop = da.memop | MO_ALIGN_64;
eight = tcg_const_tl(8);
for (i = 0; ; ++i) {
tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
- da.mem_idx, da.memop);
+ da.mem_idx, memop);
if (i == 7) {
break;
}
tcg_gen_add_tl(addr, addr, eight);
+ memop = da.memop;
}
tcg_temp_free(eight);
} else {
@@ -2488,20 +2491,23 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
case GET_ASI_BLOCK:
/* Valid for stdfa on aligned registers only. */
if (size == 8 && (rd & 7) == 0) {
+ TCGMemOp memop;
TCGv eight;
int i;
- gen_check_align(addr, 0x3f);
gen_address_mask(dc, addr);
+ /* The first operation checks required alignment. */
+ memop = da.memop | MO_ALIGN_64;
eight = tcg_const_tl(8);
for (i = 0; ; ++i) {
tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
- da.mem_idx, da.memop);
+ da.mem_idx, memop);
if (i == 7) {
break;
}
tcg_gen_add_tl(addr, addr, eight);
+ memop = da.memop;
}
tcg_temp_free(eight);
} else {
@@ -2539,9 +2545,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int
insn, int rd)
return;
case GET_ASI_DTWINX:
- gen_check_align(addr, 15);
gen_address_mask(dc, addr);
- tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop);
+ tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
tcg_gen_addi_tl(addr, addr, 8);
tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop);
break;
@@ -2594,9 +2599,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv
addr,
break;
case GET_ASI_DTWINX:
- gen_check_align(addr, 15);
gen_address_mask(dc, addr);
- tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop);
+ tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
tcg_gen_addi_tl(addr, addr, 8);
tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop);
break;
@@ -5468,7 +5472,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
- gen_check_align(cpu_addr, 7);
gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
}
break;
--
2.7.4
- [Qemu-devel] [PATCH v2 00/15] target-sparc improvements, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 01/15] target-sparc: Use overalignment flags for twinx and block asis,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 03/15] target-sparc: Add MMU_PHYS_IDX, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 05/15] target-sparc: Handle more twinx asis, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 02/15] target-sparc: Introduce cpu_raise_exception_ra, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 06/15] target-sparc: Implement swap_asi inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 07/15] target-sparc: Implement ldstub_asi inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 09/15] target-sparc: Implement BCOPY/BFILL inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 08/15] target-sparc: Implement cas_asi/casx_asi inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 12/15] target-sparc: Allow 4-byte alignment on fp mem ops, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 15/15] target-sparc: Use tcg_gen_atomic_cmpxchg_tl, Richard Henderson, 2016/10/18