[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 08/15] tcg/ppc: Implement field extraction opcodes
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 08/15] tcg/ppc: Implement field extraction opcodes |
Date: |
Sat, 15 Oct 2016 20:37:43 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc/tcg-target.h | 4 ++--
tcg/ppc/tcg-target.inc.c | 10 ++++++++++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index c765d3e..b42c57a 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -69,7 +69,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 1
#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
-#define TCG_TARGET_HAS_extract_i32 0
+#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
@@ -102,7 +102,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i64 1
#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_deposit_i64 1
-#define TCG_TARGET_HAS_extract_i64 0
+#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index a3262cf..7ec54a2 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -2396,6 +2396,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args,
}
break;
+ case INDEX_op_extract_i32:
+ tcg_out_rlw(s, RLWINM, args[0], args[1],
+ 32 - args[2], 32 - args[3], 31);
+ break;
+ case INDEX_op_extract_i64:
+ tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
+ break;
+
case INDEX_op_movcond_i32:
tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
args[3], args[4], const_args[2]);
@@ -2530,6 +2538,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
+ { INDEX_op_extract_i32, { "r", "r" } },
{ INDEX_op_muluh_i32, { "r", "r", "r" } },
{ INDEX_op_mulsh_i32, { "r", "r", "r" } },
@@ -2585,6 +2594,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
{ INDEX_op_deposit_i64, { "r", "0", "rZ" } },
+ { INDEX_op_extract_i64, { "r", "r" } },
{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
{ INDEX_op_muluh_i64, { "r", "r", "r" } },
--
2.7.4
- [Qemu-devel] [PATCH 00/15] tcg field extract primitives, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 01/15] tcg: Add field extraction primitives, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 03/15] tcg/aarch64: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 02/15] tcg: Minor adjustments to deposit expanders, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 04/15] tcg/arm: Move isa detection to tcg-target.h, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 05/15] tcg/arm: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 06/15] tcg/i386: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 07/15] tcg/mips: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 08/15] tcg/ppc: Implement field extraction opcodes,
Richard Henderson <=
- [Qemu-devel] [PATCH 09/15] tcg/s390: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 10/15] target-alpha: Use deposit and extract ops, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 11/15] target-arm: Use tcg_gen_*extract, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 12/15] target-i386: Use tcg_gen_extract_tl, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 13/15] target-mips: Use tcg_gen_extract_*, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 14/15] target-ppc: Use tcg_gen_extract_*, Richard Henderson, 2016/10/15