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[Qemu-devel] [PATCH v3 3/4] target-arm: Comments to mark location of pen
From: |
Thomas Hanson |
Subject: |
[Qemu-devel] [PATCH v3 3/4] target-arm: Comments to mark location of pending work for 56 bit addresses |
Date: |
Wed, 12 Oct 2016 13:50:52 -0600 |
Certain instructions which can not directly load a tagged address value
may trigger a corner case when the address size is 56 bits. This is
because incrementing or offsetting from the current PC can cause an
arithetic roll-over into the tag bits. Per the ARM ARM spec, these cases
should also be addressed by cleaning up the tag field.
Signed-off-by: Thomas Hanson <address@hidden>
---
target-arm/translate-a64.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 8321218..b4a4b72 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1232,6 +1232,9 @@ static inline AArch64DecodeFn *lookup_disas_fn(const
AArch64DecodeTable *table,
*/
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
{
+ /*If/when address size is 56 bits, this could overflow into address tag
+ * byte, and that byte should be fixed per ARM ARM spec.
+ */
uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
if (insn & (1U << 31)) {
@@ -1259,6 +1262,9 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t
insn)
sf = extract32(insn, 31, 1);
op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
rt = extract32(insn, 0, 5);
+ /*If/when address size is 56 bits, this could overflow into address tag
+ * byte, and that byte should be fixed per ARM ARM spec.
+ */
addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
tcg_cmp = read_cpu_reg(s, rt, sf);
@@ -1287,6 +1293,9 @@ static void disas_test_b_imm(DisasContext *s, uint32_t
insn)
bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
+ /*If/when address size is 56 bits, this could overflow into address tag
+ * byte, and that byte should be fixed per ARM ARM spec.
+ */
addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
rt = extract32(insn, 0, 5);
@@ -1316,6 +1325,9 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t
insn)
unallocated_encoding(s);
return;
}
+ /*If/when address size is 56 bits, this could overflow into address tag
+ * byte, and that byte should be fixed per ARM ARM spec.
+ */
addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
cond = extract32(insn, 0, 4);
--
1.9.1
- [Qemu-devel] [PATCH v3 0/4] target-arm: Handle tagged addresses when loading PC, Thomas Hanson, 2016/10/12
- [Qemu-devel] [PATCH v3 1/4] target-arm: Infrastucture changes to enable handling of tagged address loading into PC, Thomas Hanson, 2016/10/12
- [Qemu-devel] [PATCH v3 3/4] target-arm: Comments to mark location of pending work for 56 bit addresses,
Thomas Hanson <=
- [Qemu-devel] [PATCH v3 4/4] target-arm: Comments added to identify cases in a switch, Thomas Hanson, 2016/10/12
- [Qemu-devel] [PATCH v3 2/4] target-arm: Code changes to implement overwrite of tag field on PC load, Thomas Hanson, 2016/10/12
- Re: [Qemu-devel] [PATCH v3 0/4] target-arm: Handle tagged addresses when loading PC, Tom Hanson, 2016/10/13
- Re: [Qemu-devel] [PATCH v3 0/4] target-arm: Handle tagged addresses when loading PC, Peter Maydell, 2016/10/17