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Re: [Qemu-devel] [PATCH 00/16] target-sparc improvements
From: |
no-reply |
Subject: |
Re: [Qemu-devel] [PATCH 00/16] target-sparc improvements |
Date: |
Mon, 10 Oct 2016 10:02:48 -0700 (PDT) |
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH 00/16] target-sparc improvements
Message-id: address@hidden
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/address@hidden -> patchew/address@hidden
* [new tag] patchew/address@hidden -> patchew/address@hidden
* [new tag] patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
4974aa6 target-sparc: Use tcg_gen_atomic_cmpxchg_tl
b769d76 target-sparc: Use tcg_gen_atomic_xchg_tl
8ba7e23 target-sparc: Optmize writeback of cpu_cond
ac44dbe target-sparc: Remove MMU_MODE*_SUFFIX
9ad35ee target-sparc: Allow 4-byte alignment on fp mem ops
ee1cd04 target-sparc: Implement ldqf and stqf inline
105cd23 target-sparc: Remove asi helper code handled inline
8e2be2e target-sparc: Implement BCOPY/BFILL inline
38cbb5d target-sparc: Implement cas_asi/casx_asi inline
6ca4c14 target-sparc: Implement ldstub_asi inline
d90214c target-sparc: Implement swap_asi inline
e652593 target-sparc: Handle more twinx asis
9af8f40 target-sparc: Use MMU_PHYS_IDX for bypass asis
1f3996d target-sparc: Add MMU_PHYS_IDX
38fa924 target-sparc: Introduce cpu_raise_exception_ra
30abd6e target-sparc: Use overalignment flags for twinx and block asis
=== OUTPUT BEGIN ===
Checking PATCH 1/16: target-sparc: Use overalignment flags for twinx and block
asis...
Checking PATCH 2/16: target-sparc: Introduce cpu_raise_exception_ra...
Checking PATCH 3/16: target-sparc: Add MMU_PHYS_IDX...
Checking PATCH 4/16: target-sparc: Use MMU_PHYS_IDX for bypass asis...
Checking PATCH 5/16: target-sparc: Handle more twinx asis...
Checking PATCH 6/16: target-sparc: Implement swap_asi inline...
Checking PATCH 7/16: target-sparc: Implement ldstub_asi inline...
Checking PATCH 8/16: target-sparc: Implement cas_asi/casx_asi inline...
Checking PATCH 9/16: target-sparc: Implement BCOPY/BFILL inline...
Checking PATCH 10/16: target-sparc: Remove asi helper code handled inline...
Checking PATCH 11/16: target-sparc: Implement ldqf and stqf inline...
Checking PATCH 12/16: target-sparc: Allow 4-byte alignment on fp mem ops...
ERROR: spaces required around that '/' (ctx:VxV)
#47: FILE: target-sparc/translate.c:2484:
+ tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
^
ERROR: spaces required around that '+' (ctx:VxV)
#47: FILE: target-sparc/translate.c:2484:
+ tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
^
total: 2 errors, 0 warnings, 175 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 13/16: target-sparc: Remove MMU_MODE*_SUFFIX...
Checking PATCH 14/16: target-sparc: Optmize writeback of cpu_cond...
Checking PATCH 15/16: target-sparc: Use tcg_gen_atomic_xchg_tl...
Checking PATCH 16/16: target-sparc: Use tcg_gen_atomic_cmpxchg_tl...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden
- [Qemu-devel] [PATCH 07/16] target-sparc: Implement ldstub_asi inline, (continued)
- [Qemu-devel] [PATCH 07/16] target-sparc: Implement ldstub_asi inline, Richard Henderson, 2016/10/10
- [Qemu-devel] [PATCH 11/16] target-sparc: Implement ldqf and stqf inline, Richard Henderson, 2016/10/10
- [Qemu-devel] [PATCH 13/16] target-sparc: Remove MMU_MODE*_SUFFIX, Richard Henderson, 2016/10/10
- [Qemu-devel] [PATCH 08/16] target-sparc: Implement cas_asi/casx_asi inline, Richard Henderson, 2016/10/10
- [Qemu-devel] [PATCH 09/16] target-sparc: Implement BCOPY/BFILL inline, Richard Henderson, 2016/10/10
- [Qemu-devel] [PATCH 12/16] target-sparc: Allow 4-byte alignment on fp mem ops, Richard Henderson, 2016/10/10
- [Qemu-devel] [PATCH 14/16] target-sparc: Optmize writeback of cpu_cond, Richard Henderson, 2016/10/10
- [Qemu-devel] [PATCH 10/16] target-sparc: Remove asi helper code handled inline, Richard Henderson, 2016/10/10
- [Qemu-devel] [PATCH 15/16] target-sparc: Use tcg_gen_atomic_xchg_tl, Richard Henderson, 2016/10/10
- [Qemu-devel] [PATCH 16/16] target-sparc: Use tcg_gen_atomic_cmpxchg_tl, Richard Henderson, 2016/10/10
- Re: [Qemu-devel] [PATCH 00/16] target-sparc improvements,
no-reply <=
- Re: [Qemu-devel] [PATCH 00/16] target-sparc improvements, Mark Cave-Ayland, 2016/10/11