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[Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1 |
Date: |
Thu, 6 Oct 2016 14:21:05 +0100 |
MDCCINT_EL1 is part of the DCC debugger communication
channel between the CPU and an attached external debugger.
QEMU doesn't implement this, but since Linux may try
to access this register we need to provide at least
a dummy implementation.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 25f612d..23792ab 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4060,6 +4060,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_NOP },
+ /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
+ * Channel but Linux may try to access this register. The 32-bit
+ * alias is DBGDCCINT.
+ */
+ { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .accessfn = access_tda,
+ .type = ARM_CP_NOP },
REGINFO_SENTINEL
};
--
2.7.4
- [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support, Peter Maydell, 2016/10/06
- [Qemu-devel] [PATCH 3/3] hw/intc/arm_gicv3: Fix ICC register tracepoints, Peter Maydell, 2016/10/06
- [Qemu-devel] [PATCH 2/3] target-arm: Add trace events for the generic timers, Peter Maydell, 2016/10/06
- [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1,
Peter Maydell <=
- Re: [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support, Edgar E. Iglesias, 2016/10/06
- Re: [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support, Peter Maydell, 2016/10/11
- Re: [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support, no-reply, 2016/10/11