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Re: [Qemu-devel] [PATCH 3/6] aspeed: extend the number of host SPI contr
From: |
Andrew Jeffery |
Subject: |
Re: [Qemu-devel] [PATCH 3/6] aspeed: extend the number of host SPI controllers |
Date: |
Wed, 05 Oct 2016 10:02:10 +1030 |
On Tue, 2016-09-27 at 13:57 +0200, Cédric Le Goater wrote:
> The AST2500 SoC has two. Let's prepare ground for the next changes
> which will add the required definitions for the second host SPI
> controller.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
> ---
> hw/arm/aspeed.c | 2 +-
> hw/arm/aspeed_soc.c | 44 +++++++++++++++++++++++++++++---------------
> include/hw/arm/aspeed_soc.h | 6 +++++-
> 3 files changed, 35 insertions(+), 17 deletions(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 4bb33cbb5e70..c7206fda6d85 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -129,7 +129,7 @@ static void aspeed_board_init(MachineState *machine,
> &error_abort);
>
> aspeed_board_init_flashes(&bmc->soc.fmc, "n25q256a", &error_abort);
> - aspeed_board_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort);
> + aspeed_board_init_flashes(&bmc->soc.spi[0], "mx25l25635e", &error_abort);
>
> aspeed_board_binfo.kernel_filename = machine->kernel_filename;
> aspeed_board_binfo.initrd_filename = machine->initrd_filename;
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 80ad7322bde2..b3103f337374 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -37,10 +37,17 @@ static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37,
> 38, 39, };
> #define AST2400_SDRAM_BASE 0x40000000
> #define AST2500_SDRAM_BASE 0x80000000
>
> +static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
> +
> +static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE };
> +
> static const AspeedSoCInfo aspeed_socs[] = {
> - { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE },
> - { "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE },
> - { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE },
> + { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,
> + 1, aspeed_soc_ast2400_spi_bases },
> + { "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,
> + 1, aspeed_soc_ast2400_spi_bases },
> + { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE,
> + 1, aspeed_soc_ast2500_spi_bases },
> };
>
> /*
> @@ -72,6 +79,7 @@ static void aspeed_soc_init(Object *obj)
> {
> AspeedSoCState *s = ASPEED_SOC(obj);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + int i;
>
> s->cpu = cpu_arm_init(sc->info->cpu_model);
>
> @@ -101,9 +109,11 @@ static void aspeed_soc_init(Object *obj)
> object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
> qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
>
> - object_initialize(&s->spi, sizeof(s->spi), "aspeed.smc.spi");
> - object_property_add_child(obj, "spi", OBJECT(&s->spi), NULL);
> - qdev_set_parent_bus(DEVICE(&s->spi), sysbus_get_default());
> + for (i = 0; i < sc->info->spis_num; i++) {
> + object_initialize(&s->spi[i], sizeof(s->spi[i]), "aspeed.smc.spi");
> + object_property_add_child(obj, "spi", OBJECT(&s->spi[i]), NULL);
> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
> + }
>
> object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
> object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
> @@ -118,6 +128,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error
> **errp)
> {
> int i;
> AspeedSoCState *s = ASPEED_SOC(dev);
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> Error *err = NULL, *local_err = NULL;
>
> /* IO space */
> @@ -190,16 +201,19 @@ static void aspeed_soc_realize(DeviceState *dev, Error
> **errp)
> qdev_get_gpio_in(DEVICE(&s->vic), 19));
>
> /* SPI */
> - object_property_set_int(OBJECT(&s->spi), 1, "num-cs", &err);
> - object_property_set_bool(OBJECT(&s->spi), true, "realized", &local_err);
> - error_propagate(&err, local_err);
> - if (err) {
> - error_propagate(errp, err);
> - return;
> + for (i = 0; i < sc->info->spis_num; i++) {
> + object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
> + &local_err);
> + error_propagate(&err, local_err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
> sc->info->spi_bases[i]);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
> + s->spi[i].ctrl->flash_window_base);
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, ASPEED_SOC_SPI_BASE);
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1,
> - s->spi.ctrl->flash_window_base);
>
> /* SDMC - SDRAM Memory Controller */
> object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 7359e25fce49..f26a9f043983 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -20,6 +20,8 @@
> #include "hw/i2c/aspeed_i2c.h"
> #include "hw/ssi/aspeed_smc.h"
>
> +#define ASPEED_SPIS_NUM 2
> +
> typedef struct AspeedSoCState {
> /*< private >*/
> DeviceState parent;
> @@ -32,7 +34,7 @@ typedef struct AspeedSoCState {
> AspeedI2CState i2c;
> AspeedSCUState scu;
> AspeedSMCState fmc;
> - AspeedSMCState spi;
> + AspeedSMCState spi[ASPEED_SPIS_NUM];
> AspeedSDMCState sdmc;
> } AspeedSoCState;
>
> @@ -44,6 +46,8 @@ typedef struct AspeedSoCInfo {
> const char *cpu_model;
> uint32_t silicon_rev;
> hwaddr sdram_base;
> + int spis_num;
> + const hwaddr *spi_bases;
> } AspeedSoCInfo;
>
> typedef struct AspeedSoCClass {
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