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[Qemu-devel] [PATCH 18/29] target-sparc: use SparcV9MMU type for sparc64
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH 18/29] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs |
Date: |
Sat, 1 Oct 2016 12:05:22 +0200 |
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target-sparc/cpu.h | 48 +++++++++++++++++-----------------------------
target-sparc/ldst_helper.c | 8 ++++----
target-sparc/machine.c | 4 ++--
3 files changed, 24 insertions(+), 36 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 41002af..7b77d26 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -396,7 +396,22 @@ struct CPUTimer
typedef struct CPUTimer CPUTimer;
typedef struct CPUSPARCState CPUSPARCState;
-
+#if defined(TARGET_SPARC64)
+typedef union {
+ uint64_t mmuregs[16];
+ struct {
+ uint64_t tsb_tag_target;
+ uint64_t mmu_primary_context;
+ uint64_t mmu_secondary_context;
+ uint64_t sfsr;
+ uint64_t sfar;
+ uint64_t tsb;
+ uint64_t tag_access;
+ uint64_t virtual_watchpoint;
+ uint64_t physical_watchpoint;
+ };
+} SparcV9MMU;
+#endif
struct CPUSPARCState {
target_ulong gregs[8]; /* general registers */
target_ulong *regwptr; /* pointer to current register window */
@@ -446,35 +461,8 @@ struct CPUSPARCState {
uint64_t lsu;
#define DMMU_E 0x8
#define IMMU_E 0x4
- //typedef struct SparcMMU
- union {
- uint64_t immuregs[16];
- struct {
- uint64_t tsb_tag_target;
- uint64_t unused_mmu_primary_context; // use DMMU
- uint64_t unused_mmu_secondary_context; // use DMMU
- uint64_t sfsr;
- uint64_t sfar;
- uint64_t tsb;
- uint64_t tag_access;
- uint64_t virtual_watchpoint;
- uint64_t physical_watchpoint;
- } immu;
- };
- union {
- uint64_t dmmuregs[16];
- struct {
- uint64_t tsb_tag_target;
- uint64_t mmu_primary_context;
- uint64_t mmu_secondary_context;
- uint64_t sfsr;
- uint64_t sfar;
- uint64_t tsb;
- uint64_t tag_access;
- uint64_t virtual_watchpoint;
- uint64_t physical_watchpoint;
- } dmmu;
- };
+ SparcV9MMU immu;
+ SparcV9MMU dmmu;
SparcTLBEntry itlb[64];
SparcTLBEntry dtlb[64];
uint32_t mmu_version;
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 11ca74e..5e79627 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1931,7 +1931,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr,
target_ulong val,
int reg = (addr >> 3) & 0xf;
uint64_t oldreg;
- oldreg = env->immuregs[reg];
+ oldreg = env->immu.mmuregs[reg];
switch (reg) {
case 0: /* RO */
return;
@@ -1962,7 +1962,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr,
target_ulong val,
break;
}
- if (oldreg != env->immuregs[reg]) {
+ if (oldreg != env->immu.mmuregs[reg]) {
DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
}
@@ -1996,7 +1996,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr,
target_ulong val,
int reg = (addr >> 3) & 0xf;
uint64_t oldreg;
- oldreg = env->dmmuregs[reg];
+ oldreg = env->dmmu.mmuregs[reg];
switch (reg) {
case 0: /* RO */
case 4:
@@ -2039,7 +2039,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr,
target_ulong val,
break;
}
- if (oldreg != env->dmmuregs[reg]) {
+ if (oldreg != env->dmmu.mmuregs[reg]) {
DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
}
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index 59c92f7..bd63841 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -151,8 +151,8 @@ const VMStateDescription vmstate_sparc_cpu = {
VMSTATE_UINT64_ARRAY(env.mmubpregs, SPARCCPU, 4),
#else
VMSTATE_UINT64(env.lsu, SPARCCPU),
- VMSTATE_UINT64_ARRAY(env.immuregs, SPARCCPU, 16),
- VMSTATE_UINT64_ARRAY(env.dmmuregs, SPARCCPU, 16),
+ VMSTATE_UINT64_ARRAY(env.immu.mmuregs, SPARCCPU, 16),
+ VMSTATE_UINT64_ARRAY(env.dmmu.mmuregs, SPARCCPU, 16),
VMSTATE_STRUCT_ARRAY(env.itlb, SPARCCPU, 64, 0,
vmstate_tlb_entry, SparcTLBEntry),
VMSTATE_STRUCT_ARRAY(env.dtlb, SPARCCPU, 64, 0,
--
2.7.2
- [Qemu-devel] [PATCH 12/29] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, (continued)
- [Qemu-devel] [PATCH 12/29] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 13/29] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 14/29] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 15/29] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 16/29] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 17/29] target-sparc: replace the last tlb entry when no free entries left, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 18/29] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH 19/29] target-sparc: implement UA2005 TSB Pointers, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 21/29] target-sparc: allow 256M sized pages, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 20/29] target-sparc: simplify ultrasparc_tsb_pointer, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 22/29] target-sparc: implement auto-demapping for UA2005 CPUs, Artyom Tarasenko, 2016/10/01