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[Qemu-devel] [PULL 45/45] spapr_pci: Add numa node id
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 45/45] spapr_pci: Add numa node id |
Date: |
Fri, 23 Sep 2016 17:15:21 +1000 |
From: Alexey Kardashevskiy <address@hidden>
This adds a numa id property to a PHB to allow linking passed PCI device
to CPU/memory. It is up to the management stack to do CPU/memory pinning
to the node with the actual PCI device.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
[dwg: Renamed property from "node" to "numa_node" to match the similar
one in the pxb device]
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/spapr_pci.c | 13 +++++++++++++
include/hw/pci-host/spapr.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 949c44f..4f00865 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -47,6 +47,7 @@
#include "sysemu/device_tree.h"
#include "sysemu/kvm.h"
#include "sysemu/hostmem.h"
+#include "sysemu/numa.h"
#include "hw/vfio/vfio.h"
@@ -1544,6 +1545,7 @@ static Property spapr_phb_properties[] = {
DEFINE_PROP_BOOL("ddw", sPAPRPHBState, ddw_enabled, true),
DEFINE_PROP_UINT64("pgsz", sPAPRPHBState, page_size_mask,
(1ULL << 12) | (1ULL << 16)),
+ DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1),
DEFINE_PROP_END_OF_LIST(),
};
@@ -1805,6 +1807,11 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb,
cpu_to_be32(1),
cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW)
};
+ uint32_t associativity[] = {cpu_to_be32(0x4),
+ cpu_to_be32(0x0),
+ cpu_to_be32(0x0),
+ cpu_to_be32(0x0),
+ cpu_to_be32(phb->numa_node)};
sPAPRTCETable *tcet;
PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
sPAPRFDT s_fdt;
@@ -1837,6 +1844,12 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb,
&ddw_extensions, sizeof(ddw_extensions)));
}
+ /* Advertise NUMA via ibm,associativity */
+ if (nb_numa_nodes > 1) {
+ _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity,
+ sizeof(associativity)));
+ }
+
/* Build the interrupt-map, this must matches what is done
* in pci_spapr_map_irq
*/
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index 1a2b11b..30dbd46 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -75,6 +75,8 @@ struct sPAPRPHBState {
bool ddw_enabled;
uint64_t page_size_mask;
uint64_t dma64_win_addr;
+
+ uint32_t numa_node;
};
#define SPAPR_PCI_MAX_INDEX 255
--
2.7.4
- [Qemu-devel] [PULL 40/45] ppc/xics: account correct irq status, (continued)
- [Qemu-devel] [PULL 40/45] ppc/xics: account correct irq status, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 06/45] target-ppc: add vector bit permute doubleword instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 08/45] ppc: Fix signal delivery in ppc-user and ppc64-user, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 14/45] adb.c: add support for QKeyCode, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 34/45] target-ppc: implement darn instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 39/45] Enable H_CLEAR_MOD and H_CLEAR_REF hypercalls on KVM/PPC64., David Gibson, 2016/09/23
- [Qemu-devel] [PULL 38/45] target-ppc: tlbie/tlbivax should have global effect, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 10/45] libqos: define SPAPR libqos functions, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 41/45] ppc/xics: An ICS with offset 0 is assumed to be uninitialized, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 25/45] target-ppc: consolidate store operations, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 45/45] spapr_pci: Add numa node id,
David Gibson <=
- [Qemu-devel] [PULL 05/45] target-ppc: add vector count trailing zeros instructions, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 37/45] target-ppc: add flag in check_tlb_flush(), David Gibson, 2016/09/23
- [Qemu-devel] [PULL 44/45] monitor: fix crash for platforms without a CPU 0, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 11/45] tests: add RTAS command in the protocol, David Gibson, 2016/09/23
- Re: [Qemu-devel] [PULL 00/45] ppc-for-2.8 queue 20160923, no-reply, 2016/09/23
- Re: [Qemu-devel] [PULL 00/45] ppc-for-2.8 queue 20160923, Peter Maydell, 2016/09/23