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[Qemu-devel] [PULL 31/45] target-ppc: add xxspltib instruction
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 31/45] target-ppc: add xxspltib instruction |
Date: |
Fri, 23 Sep 2016 17:15:07 +1000 |
From: Nikunj A Dadhania <address@hidden>
xxspltib: VSX Vector Splat Immediate Byte
Copy the immediate byte in each byte of target VSR
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 2 ++
target-ppc/translate/vsx-impl.inc.c | 20 ++++++++++++++++++++
target-ppc/translate/vsx-ops.inc.c | 5 +++++
3 files changed, 27 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ecc1674..133c531 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -591,6 +591,8 @@ EXTRACT_HELPER(DM, 8, 2);
EXTRACT_HELPER(UIM, 16, 2);
EXTRACT_HELPER(SHW, 8, 2);
EXTRACT_HELPER(SP, 19, 2);
+EXTRACT_HELPER(IMM8, 11, 8);
+
/*****************************************************************************/
/* PowerPC instructions table */
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index 99cabb2..67f5621 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -647,6 +647,26 @@ static void gen_xxspltw(DisasContext *ctx)
tcg_temp_free_i64(b2);
}
+#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
+
+static void gen_xxspltib(DisasContext *ctx)
+{
+ unsigned char uim8 = IMM8(ctx->opcode);
+ if (xS(ctx->opcode) < 32) {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ }
+ tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), pattern(uim8));
+ tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), pattern(uim8));
+}
+
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;
diff --git a/target-ppc/translate/vsx-ops.inc.c
b/target-ppc/translate/vsx-ops.inc.c
index 8b9da65..62a6251 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -20,6 +20,10 @@ GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800,
PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
#endif
+#define GEN_XX1FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+
#define GEN_XX2FORM(name, opc2, opc3, fl2) \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
@@ -222,6 +226,7 @@ VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
+GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
#define GEN_XXSEL_ROW(opc3) \
--
2.7.4
- [Qemu-devel] [PULL 20/45] spapr_llan: convert to trace framework instead of DPRINTF, (continued)
- [Qemu-devel] [PULL 20/45] spapr_llan: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 19/45] spapr_vio: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 18/45] spapr_rtas: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 21/45] spapr_vscsi: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 24/45] target-ppc: convert ld[16, 32, 64]ur to use new macro, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 22/45] target-ppc: consolidate load operations, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 23/45] target-ppc: convert ld64 to use new macro, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 29/45] target-ppc: move out stqcx impementation, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 28/45] target-ppc: consolidate load with reservation, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 27/45] target-ppc: convert st[16, 32, 64]r to use new macro, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 31/45] target-ppc: add xxspltib instruction,
David Gibson <=
- [Qemu-devel] [PULL 30/45] target-ppc: consolidate store conditional, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 07/45] target-ppc: add vector permute right indexed instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 33/45] target-ppc: add stxsi[bh]x instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 36/45] target-ppc: add TLB_NEED_LOCAL_FLUSH flag, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 35/45] spapr: Introduce sPAPRCPUCoreClass, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 26/45] target-ppc: convert st64 to use new macro, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 42/45] ppc/kvm: Mark 64kB page size support as disabled if not available, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 32/45] target-ppc: add lxsi[bw]zx instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 43/45] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 40/45] ppc/xics: account correct irq status, David Gibson, 2016/09/23