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[Qemu-devel] [PULL 12/36] aspeed: calculate the RAM size bits at realize
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/36] aspeed: calculate the RAM size bits at realize time |
Date: |
Thu, 22 Sep 2016 18:21:51 +0100 |
From: Cédric Le Goater <address@hidden>
There is no need to do this at each reset as the RAM size will not
change.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/misc/aspeed_sdmc.c | 16 ++++++++++++++--
include/hw/misc/aspeed_sdmc.h | 1 +
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 244e5c0..1d28252 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -192,7 +192,7 @@ static void aspeed_sdmc_reset(DeviceState *dev)
case AST2400_A0_SILICON_REV:
s->regs[R_CONF] |=
ASPEED_SDMC_VGA_COMPAT |
- ASPEED_SDMC_DRAM_SIZE(ast2400_rambits());
+ ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
break;
case AST2500_A0_SILICON_REV:
@@ -200,7 +200,7 @@ static void aspeed_sdmc_reset(DeviceState *dev)
s->regs[R_CONF] |=
ASPEED_SDMC_HW_VERSION(1) |
ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
- ASPEED_SDMC_DRAM_SIZE(ast2500_rambits());
+ ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
break;
default:
@@ -219,6 +219,18 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error
**errp)
return;
}
+ switch (s->silicon_rev) {
+ case AST2400_A0_SILICON_REV:
+ s->ram_bits = ast2400_rambits();
+ break;
+ case AST2500_A0_SILICON_REV:
+ case AST2500_A1_SILICON_REV:
+ s->ram_bits = ast2500_rambits();
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
TYPE_ASPEED_SDMC, 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
index 7e081f6..df7dce0 100644
--- a/include/hw/misc/aspeed_sdmc.h
+++ b/include/hw/misc/aspeed_sdmc.h
@@ -25,6 +25,7 @@ typedef struct AspeedSDMCState {
uint32_t regs[ASPEED_SDMC_NR_REGS];
uint32_t silicon_rev;
+ uint32_t ram_bits;
} AspeedSDMCState;
--
2.7.4
- [Qemu-devel] [PULL 00/36] target-arm queue, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 13/36] aspeed: use error_report instead of LOG_GUEST_ERROR, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 10/36] arm: add support for an ast2500 evaluation board, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 12/36] aspeed: calculate the RAM size bits at realize time,
Peter Maydell <=
- [Qemu-devel] [PULL 16/36] hw/ptimer: Actually stop the timer in case of error, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 07/36] palmetto-bmc: add board specific configuration, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 08/36] hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 18/36] hw/ptimer: Suppress error messages under qtest, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 03/36] ast2400: replace ast2400 with aspeed_soc, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 15/36] aspeed: allocate RAM after the memory controller has checked the size, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 09/36] aspeed: add a ast2500 SoC and support to the SCU and SDMC controllers, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 22/36] cadence_gem: Add support for screening, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 25/36] xlnx-zynqmp: Set the number of priority queues, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 11/36] palmetto-bmc: remove extra no_sdcard assignement, Peter Maydell, 2016/09/22