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Re: [Qemu-devel] [PATCH v4 30/35] target-arm: emulate aarch64's LL/SC us
From: |
Emilio G. Cota |
Subject: |
Re: [Qemu-devel] [PATCH v4 30/35] target-arm: emulate aarch64's LL/SC using cmpxchg helpers |
Date: |
Fri, 16 Sep 2016 20:16:51 -0400 |
User-agent: |
Mutt/1.5.23 (2014-03-12) |
On Fri, Sep 16, 2016 at 10:46:52 -0700, Richard Henderson wrote:
(snip)
> +/* Returns 0 on success; 1 otherwise. */
> +uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
> + uint64_t new_lo, uint64_t new_hi)
> +{
> + uintptr_t ra = GETPC();
> + Int128 oldv, cmpv, newv;
> + bool success;
> +
> + cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
> + newv = int128_make128(new_lo, new_hi);
> +
> + if (parallel_cpus) {
> +#ifndef CONFIG_ATOMIC128
> + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
> +#else
> + int mem_idx = cpu_mmu_index(env, false);
> + TCGMemOpIdx oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
> + oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra);
> + success = int128_eq(oldv, cmpv);
> +#endif
> + } else {
> + uint64_t o0, o1;
> +
> +#ifdef CONFIG_USER_ONLY
> + /* ??? Enforce alignment. */
> + uint64_t *haddr = g2h(addr);
> + o0 = ldq_le_p(haddr + 0);
> + o1 = ldq_le_p(haddr + 1);
> + oldv = int128_make128(o0, o1);
> +
> + success = int128_eq(oldv, cmpv);
> + if (success) {
> + stq_le_p(haddr + 0, int128_getlo(newv));
> + stq_le_p(haddr + 8, int128_gethi(newv));
Shouldn't this be + 1 instead, just like the above load?
If so, the same applies to the store in the _be function.
Thanks,
Emilio
- [Qemu-devel] [PATCH v4 13/35] tcg: Add atomic helpers, (continued)
- [Qemu-devel] [PATCH v4 13/35] tcg: Add atomic helpers, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 18/35] target-i386: emulate LOCK'ed OP instructions using atomic helpers, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 20/35] target-i386: emulate LOCK'ed NOT using atomic helper, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 21/35] target-i386: emulate LOCK'ed NEG using cmpxchg helper, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 22/35] target-i386: emulate LOCK'ed XADD using atomic helper, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 31/35] linux-user: remove handling of ARM's EXCP_STREX, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 28/35] target-arm: emulate LL/SC using cmpxchg helpers, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 29/35] target-arm: emulate SWP with atomic_xchg helper, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 33/35] target-arm: remove EXCP_STREX + cpu_exclusive_{test, info}, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 30/35] target-arm: emulate aarch64's LL/SC using cmpxchg helpers, Richard Henderson, 2016/09/16
- Re: [Qemu-devel] [PATCH v4 30/35] target-arm: emulate aarch64's LL/SC using cmpxchg helpers,
Emilio G. Cota <=
- [Qemu-devel] [PATCH v4 27/35] target-arm: Rearrange aa32 load and store functions, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 34/35] target-alpha: Introduce MMU_PHYS_IDX, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 35/35] target-alpha: Emulate LL/SC using cmpxchg helpers, Richard Henderson, 2016/09/16
- [Qemu-devel] [PATCH v4 32/35] linux-user: remove handling of aarch64's EXCP_STREX, Richard Henderson, 2016/09/16