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[Qemu-devel] [PULL v5 18/18] tcg: Optimize fence instructions
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL v5 18/18] tcg: Optimize fence instructions |
Date: |
Wed, 14 Sep 2016 09:20:13 -0700 |
From: Pranith Kumar <address@hidden>
This commit optimizes fence instructions. Two optimizations are
currently implemented: (1) unnecessary duplicate fence instructions,
and (2) merging weaker fences into a stronger fence.
[rth: Merge tcg_optimize_mb back into tcg_optimize, so that we only
loop over the opcode stream once. Merge "unrelated" weaker barriers
into one stronger barrier.]
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/optimize.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index cffe89b..9998ac7 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -542,6 +542,7 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
void tcg_optimize(TCGContext *s)
{
int oi, oi_next, nb_temps, nb_globals;
+ TCGArg *prev_mb_args = NULL;
/* Array VALS has an element for each temp.
If this temp holds a constant then its value is kept in VALS' element.
@@ -1295,5 +1296,43 @@ void tcg_optimize(TCGContext *s)
}
break;
}
+
+ /* Eliminate duplicate and redundant fence instructions. */
+ if (prev_mb_args) {
+ switch (opc) {
+ case INDEX_op_mb:
+ /* Merge two barriers of the same type into one,
+ * or a weaker barrier into a stronger one,
+ * or two weaker barriers into a stronger one.
+ * mb X; mb Y => mb X|Y
+ * mb; strl => mb; st
+ * ldaq; mb => ld; mb
+ * ldaq; strl => ld; mb; st
+ * Other combinations are also merged into a strong
+ * barrier. This is stricter than specified but for
+ * the purposes of TCG is better than not optimizing.
+ */
+ prev_mb_args[0] |= args[0];
+ tcg_op_remove(s, op);
+ break;
+
+ default:
+ /* Opcodes that end the block stop the optimization. */
+ if ((def->flags & TCG_OPF_BB_END) == 0) {
+ break;
+ }
+ /* fallthru */
+ case INDEX_op_qemu_ld_i32:
+ case INDEX_op_qemu_ld_i64:
+ case INDEX_op_qemu_st_i32:
+ case INDEX_op_qemu_st_i64:
+ case INDEX_op_call:
+ /* Opcodes that touch guest memory stop the optimization. */
+ prev_mb_args = NULL;
+ break;
+ }
+ } else if (opc == INDEX_op_mb) {
+ prev_mb_args = args;
+ }
}
}
--
2.7.4
- [Qemu-devel] [PULL v5 08/18] tcg/ia64: Add support for fence, (continued)
- [Qemu-devel] [PULL v5 08/18] tcg/ia64: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 10/18] tcg/ppc: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 11/18] tcg/s390: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 09/18] tcg/mips: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 13/18] tcg/tci: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 15/18] target-arm: Generate fences in ARMv7 frontend, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 12/18] tcg/sparc: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 14/18] target-alpha: Generate fence op, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 16/18] target-aarch64: Generate fences for aarch64, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 17/18] target-i386: Generate fences for x86, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 18/18] tcg: Optimize fence instructions,
Richard Henderson <=
- Re: [Qemu-devel] [PULL v5 00/18] tcg queued patches, Peter Maydell, 2016/09/15