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[Qemu-devel] [PULL 32/64] ppc: Don't update NIP in facility unavailable
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 32/64] ppc: Don't update NIP in facility unavailable interrupts |
Date: |
Wed, 7 Sep 2016 20:29:11 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
This is no longer necessary as the helpers will properly retrieve
the return address when needed. Also remove gen_update_current_nip()
which didn't seem to make much sense to me.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/cpu.h | 1 -
target-ppc/misc_helper.c | 9 +++++----
target-ppc/translate.c | 7 -------
target-ppc/translate_init.c | 2 --
4 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a872efb..1e808c8 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1202,7 +1202,6 @@ extern const struct VMStateDescription vmstate_ppc_cpu;
PowerPCCPU *cpu_ppc_init(const char *cpu_model);
void ppc_translate_init(void);
const char *ppc_cpu_lookup_alias(const char *alias);
-void gen_update_current_nip(void *opaque);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
index cb5ebf5..1e6e705 100644
--- a/target-ppc/misc_helper.c
+++ b/target-ppc/misc_helper.c
@@ -39,7 +39,8 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
#ifdef TARGET_PPC64
static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
- uint32_t sprn, uint32_t cause)
+ uint32_t sprn, uint32_t cause,
+ uintptr_t raddr)
{
qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
@@ -47,7 +48,7 @@ static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
cause &= FSCR_IC_MASK;
env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
- helper_raise_exception_err(env, POWERPC_EXCP_FU, 0);
+ raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
}
#endif
@@ -59,7 +60,7 @@ void helper_fscr_facility_check(CPUPPCState *env, uint32_t
bit,
/* Facility is enabled, continue */
return;
}
- raise_fu_exception(env, bit, sprn, cause);
+ raise_fu_exception(env, bit, sprn, cause, GETPC());
#endif
}
@@ -71,7 +72,7 @@ void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
/* Facility is enabled, continue */
return;
}
- raise_fu_exception(env, bit, sprn, cause);
+ raise_fu_exception(env, bit, sprn, cause, GETPC());
#endif
}
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 46b0e18..b62772b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -266,13 +266,6 @@ static inline void gen_update_nip(DisasContext *ctx,
target_ulong nip)
tcg_gen_movi_tl(cpu_nip, nip);
}
-void gen_update_current_nip(void *opaque)
-{
- DisasContext *ctx = opaque;
-
- tcg_gen_movi_tl(cpu_nip, ctx->nip);
-}
-
static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
{
TCGv_i32 t0, t1;
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 293cc3d..407ccb9 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7470,7 +7470,6 @@ static void gen_fscr_facility_check(DisasContext *ctx,
int facility_sprn,
TCGv_i32 t2 = tcg_const_i32(sprn);
TCGv_i32 t3 = tcg_const_i32(cause);
- gen_update_current_nip(ctx);
gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
tcg_temp_free_i32(t3);
@@ -7485,7 +7484,6 @@ static void gen_msr_facility_check(DisasContext *ctx, int
facility_sprn,
TCGv_i32 t2 = tcg_const_i32(sprn);
TCGv_i32 t3 = tcg_const_i32(cause);
- gen_update_current_nip(ctx);
gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
tcg_temp_free_i32(t3);
--
2.7.4
- [Qemu-devel] [PULL 00/64] ppc-for-2.8 queue 20160907, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 05/64] target-ppc: adding addpcis instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 01/64] xics_kvm: drop extra checking of kernel_xics_fd, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 03/64] target-ppc: Introduce Power9 family, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 04/64] target-ppc: Introduce POWER ISA 3.0 flag, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 07/64] target-ppc: add modulo word operations, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 02/64] hw/ppc: include fdt helper routine in a common file, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 10/64] target-ppc: add cnttzw[.] instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 11/64] target-ppc: add cmpeqb instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 06/64] target-ppc: add cmprb instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 32/64] ppc: Don't update NIP in facility unavailable interrupts,
David Gibson <=
- [Qemu-devel] [PULL 08/64] target-ppc: add modulo dword operations, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 13/64] target-ppc: add maddld instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 34/64] ppc: Don't update NIP on conditional trap instructions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 15/64] target-ppc: introduce opc4 for Expanded Opcode, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 16/64] ppc: Provide basic raise_exception_* functions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 30/64] ppc: Fix source NIP on SLB related interrupts, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 19/64] ppc: Move DFP ops out of translate.c, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 33/64] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 28/64] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 12/64] target-ppc: add setb instruction, David Gibson, 2016/09/07